Jasper Lake EDS Vol1


ID 633935
Date 01/01/2021
Public Content

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Document Table of Contents

Serial Peripheral Interface (SPI)

The SoC provides two Serial Peripheral Interfaces (SPI). The SPI0 interface consists of 3 Chip Select signals. It is allowing up to two flash memory devices (SPI0_​CS0# and SPI0_​CS1#) and one TPM device (SPI0_​CS2#) to be connected to the PCH. The SPI0 interface support either 1.8V or 3.3V.