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Testability
This chapter provides information regarding testability of on the following topics:
Intel® Processor Trace
Intel® Processor Trace (Intel® PT) is a tracing capability added to Intel® Architecture, for use in software debug and profiling. Intel® PT provides the capability for precise software control flow and timing information, with limited impact to software execution. This provides enhanced ability to debug software crashes, hangs, or other anomalies, as well as responsiveness and short-duration performance issues. Refer to the Intel® 64 Architectures Software Developer’s Manual, for more information: https://www.intel.com/content/www/us/en/products/processors.html/manuals.
JTAG
This provides information regarding the testability signals that provides access to JTAG, run control, system control, and observation resources. JTAG (TAP) ports are compatible with the IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1 and 1149.6 Specification, as detailed per device in each BSDL file. JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary Scan. Architecture (IEEE Std. 1149.1-2001).
Intel® Trace Hub
Intel® Trace Hub is a debug architecture that unifies hardware and software system visibility. Intel® Trace Hub is not merely intended for hardware debug or software debug, but full system debug. This includes debugging hardware and software as they interact and produce complex system behavior. Intel® Trace Hub defines new features and also leverages some existing debug technologies to provide a complete framework for hardware and software co-debug, software development and tuning, as well as overall system performance optimization.
Intel® Trace Hub is a set of silicon features with supported software API. The primary purpose is to collect trace data from different sources in the system and combine them into a single output stream with time-correlated to each other. Intel® Trace Hub uses common hardware interface for collecting time-correlated system traces through standard destinations. Intel® Trace Hub adopts industry standard (MIPI* STPv2) debug methodology for system debug and software development.
There are multiple destinations to receive the trace data from Intel® Trace Hub:
There are multiple trace sources planned to be supported in the platform:
- BIOS
- Intel® CSE
- AET (Architecture Event Trace)
- Power Management Event Trace
- Windows* ETW (for driver or application)
| Acronyms | Description |
|---|---|
| IEEE | Institute of Electrical and Electronics Engineers |
| I/O | Input/Output |
| I/OD | Input/Output Open Drain |
| JTAG | Joint Test Action Group |
| DCI | Direct Connect Interface |
| BSDL | Boundary Scan Description Language |
| DbC | Debug Class Devices |
| Specification | Location |
|---|---|
| IEEE Standard Test Access Port and Boundary Scan Architecture | http://standards.ieee.org/findstds/standard/1149.1-2013.html |