PMC_​ACPRESENT

I

AC Present: Used on mobile systems to determine presence of AC power or battery power.

PMC_​BATLOW_​N

I

Battery Low: An input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S3–S5 state. This signal can also be enabled to cause an SMI# when asserted. This signal must be tied high to the VCCDSW_​3p3, which will be tied to VCC_​3P3A on this platform.

PMC_​CORE_​VID0

O

PCH Core VID Bit 0: May connect to discrete VR on platform and used to control the VCCIN_​Aux rail (FIVR input) voltage.

In default mode this pin is driven high (‘1’)

PMC_​CORE_​VID1

O

PCH Core VID Bit 1: May connect to discrete VR on platform and used to control the VCCIN_​Aux rail (FIVR input) voltage.

In default mode this pin is driven high (‘1’)

CPU_​C10_​GATE_​N

O

External Power Gate control for VCCIO_​EXT and VCCPLL_​OC during C10. When asserted, VCCIO_​EXT can be 0V, however the power good indicators for these rails must remain asserted.

PMC_​DRAM_​RESET_​N

O

System Memory DRAM Reset: Active low reset signal, controls reset to the memory subsystems (DDR4/LPDDR4).

PMC_​DSW_​PWROK

IO

DSW PWROK: Power OK Indication for the VCC_​3P3A_​DSW voltage rail. This signal must be asserted no earlier than 10ms after the DSW power wells are valid.

PMC_​PCH_​PWROK

IO

PCH Power OK: When asserted, PMC_​PCH_​PWROK is an indication to the PCH that all of its core power rails have been stable for at least 5 ms. PMC_​PCH_​PWROK can be driven asynchronously. When PMC_​PCH_​PWROK is negated, the PCH asserts PMC_​PLTRST_​N.

PMC_​SYS_​RESET_​N

O

Platform Reset: The PCH asserts PMC_​PLTRST_​N to reset devices on the platform (such as SIO, LAN, processor, and so forth.). The PCH asserts PMC_​PLTRST_​N low in Sx states and when a cold, warm, or global reset occurs. The PCH de-asserts PMC_​PLTRST_​N upon exit from Sx states and the aforementioned resets. There is no guaranteed minimum assertion time for PMC_​PLTRST_​N.

PMC_​PWRBTN_​N

I

Power Button: Power button input signal. Used to wake the processor from power button press. The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PMC_​PWRBTN_​N is pressed for more than 4 seconds (default; timing is configurable), this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S3-S4 states. This signal has an internal Pull-up resistor and has an internal 16 ms de-bounce on the input.

PMC_​RSMRST_​N

I

Resume Well Reset: This signal is used for resetting the resume power plane logic. This signal must be asserted for at least 10 ms after the suspend power wells are valid. When de-asserted, this signal is an indication that the suspend power wells are stable.

PMC_​SLP_​WLAN_​N

O

WLAN Sub-System Sleep Control: When PMC_​SLP_​WLAN_​N is asserted, power can be shut off to the external wireless LAN device. PMC_​SLP_​WLAN_​N will always will be de-asserted in S0.

PMC_​SLP_​S0_​N

O

S0 Sleep Control: When PCH is idle and processor is in C10 state, this pin will assert to indicate VR controller can go into a light load mode. This signal can also be connected to an external power management controller for other power management related optimizations.

PMC_​SLP_​S3_​N

O

S3 Sleep Control: PMC_​SLP_​S3_​N is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

PMC_​SLP_​S4_​N

O

S4 Sleep Control: PMC_​SLP_​S4_​N is for power plane control. This signal shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state.

PMC_​SLP_​S5_​N

O

S5 Sleep Control: PMC_​SLP_​S5_​N is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states.

PMC_​SUSCLK

O

Suspend Clock: This clock is a digitally buffered version of the RTC clock.

PMC_​SUSPWRDNACK

O

SUSPWRDNACK: Active high. Asserted by the PCH when it does not require the PCH Primary well to be powered.

PMC_​SYS_​PWROK

I

System Power OK: This generic power good input to the PCH is driven and utilized in a platform-specific manner. While PMC_​PCH_​PWROK always indicates that the core wells of the PCH are stable, PMC_​SYS_​PWROK is used to inform the PCH that power is stable to other required system component(s) and the system is ready to start the exit from reset. (de-asserts PMC_​PLTRST_​N to the processor).

PMC_​SYS_​RESET_​N

I

System Reset: Reset button input signal to reset the processor. This pin forces an internal reset after being debounced.

PMC_​VRALERT_​N

I

VR Alert: ICC Max. throttling indicator from the PCH voltage regulators. PMC_​VRALERT_​N pin allows the VR to force throttling to prevent an over current shutdown.

PMC_​WAKE_​N

I/O

PCI Express* Wake Event in Sx:

Input Pin in Sx. Sideband wake signal on PCI Express* asserted by components requesting wake up.

PMC_​ALERT_​N

I

PD controller's USB-C interrupt request is presented to PMC as processor USB-C Mux Manager, through PMC_​ALERT_​N pin assertion.

VCCST_​OVERRIDE

O

This signal is used in Debug and Class. No usage in any of the functional scenarios.

THRMTRIP_​N

O

Thermal Trip: Asserted during a catastrophic thermal event. Platform design should restart or shut down the voltage rails after this event. For platform using discrete VR (voltage regulator) power delivery solution, there is additional platform logic required to initiate VR shut down on the platform when this signal is asserted.

PCHHOT_​N

OD

PCHHOT_​N indicates that it has exceeded some temperature limit set by BIOS. The temperature limit (programmed into the PHL register) is compared to the present temperature. If the present temperature is greater than the PHL value then the pin is asserted.