Jasper Lake EDS Vol1

Datasheet

ID Date Version Classification
633935 01/01/2021 Public Content

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Document Table of Contents
DSP

Processor IA Core Power Management

While executing code, Enhanced Intel SpeedStep® Technology and Intel® Speed Shift technology optimizes the processor’s IA core frequency and voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, deeper power C-states have longer entry and exit latencies but higher power savings.

Note:The performance configuration requires special tuning or adjustment of specific power management features.