Jasper Lake EDS Vol1
Legal Disclaimer Revision History Introduction Technologies Power Management Thermal Management Memory Graphics Display Imaging Pin Strap General Purpose Input and Output (GPIO) PCH Electrical Specification CPU Electrical Specifications Global Device IDs CPU And Device IDs Audio, Voice, and Speech Connectivity Integrated (CNVi) PCI Express* (PCIe*) Universal Serial Bus (USB) Serial ATA (SATA) Flexible I/O Storage Serial Peripheral Interface (SPI) Intel® Serial I/O Generic SPI (GSPI) Controllers Enhanced Serial Peripheral Interface (eSPI) Real Time Clock (RTC) 8254 Timers High Precision Event Timer (HPET) Intel® LPSS Inter-Integrated Circuit (I2C) Controllers Host System Management Bus (SMBus) Controller System Management Interface and SMLink System Management Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Testability SoC Pin Location
Security Technologies Branch Monitoring Counters Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word (PCLMULQDQ) Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection (SMEP) Intel® Supervisor Mode Access Protection (SMAP) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID)
Functional Description Configurable GPIO Voltage GPIO Buffer Impedance Compensation via SD3_RCOMP Programmable Hardware Debouncer Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO (TIME_SYNC) GPIO Blink (BK) and Serial Blink (SBK) Interrupt / IRQ via GPIO Requirement Native Function and TERM Bit Setting Virtual GPIO (vGPIO)
DC Specifications Display Port* Specification HDMI* Specifications embedded Display Port* Specifications 16550 8-bit Addressing - Debug Driver Compatibility MIPI* DSI Specification Memory Specifications MIPI* CSI Specifications CMOS DC Specifications GTL and Open Drain DC Specification PECI DC Characteristics
Features Supported Interrupt Generation PCI Express* Power Management Dynamic Link Throttling Port 8xh Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single- Root I/O Virtualization (SR- IOV) SERR# Generation Hot-Plug PCI Express* Lane Polarity Inversion PCI Express* Controller Lane Reversal Precision Time Measurement (PTM)
Audio, Voice, and Speech
- The Converged Audio Voice Speech (cAVS) subsystem consists of a collection of controller, DSP, memory, and link interfaces that provides the audio experience to the platform. This subsystem provides streaming of audio from the host SW to external audio codecs, with the host CPU and/or DSP providing the audio enrichment.
- The optional DSP can be enabled in the audio subsystem to provide low latency HW/FW acceleration for common audio and voice functions such as audio encode/decode, acoustic echo cancellation, noise cancellation, etc
- The cAVS is fully backward compatible with the Intel HD Audio specification, with the controller implements a number of Output Stream DMA engines and Input Stream DMA engines for data transfers, as well as a Command Output DMA engine and a Response Input DMA engine for control transfers.
- The cAVS also supports I2S audio codecs which are not Intel HD Audio standards. The General Purpose DMA engines has the ability to do simple data transfers or control transfers between system memory and the FIFO in the DSP I/O peripheral interfaces directly, however, these transfers are not optimized for power management.