Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
BIOS Decode Enable (ESPI_BDE) – Offset d8
Note that this register effects the BIOS decode regardless of whether the BIOS is
resident on LPC or SPI. The concept of Feature Space does not apply to SPI-based
flash. PCH simply decodes these ranges as memory accesses when enabled for the SPI
flash interface.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:16 | - | - | Reserved
|
15 | 1b | RO | F8-FF Enable (EF8) Enables decoding of 512K of the following BIOS range: |
14 | 1b | RW | F0-F8 Enable (EF0) Enables decoding of 512K of the following BIOS range: |
13 | 1b | RW | E8-EF Enable (EE8) Enables decoding of 512K of the following BIOS range: |
12 | 1b | RW | E0-E8 Enable (EE0) Enables decoding of 512K of the following BIOS range: |
11 | 1b | RW | D8-DF Enable (ED8) Enables decoding of 512K of the following BIOS range: |
10 | 1b | RW | D0-D7 Enable (ED0) Enables decoding of 512K of the following BIOS range: |
9 | 1b | RW | C8-CF Enable (EC8) Enables decoding of 512K of the following BIOS range: |
8 | 1b | RW | C0-C7 Enable (EC0) Enables decoding of 512K of the following BIOS range: |
7 | 1b | RW | Legacy F Segment Enable (LFE) This enables the decoding of the legacy 64KB range at F0000h - FFFFFh |
6 | 1b | RW | Legacy E Segment Enable (LEE) This enables the decoding of the legacy 64KB range at E0000h - EFFFFh |
5:4 | - | - | Reserved
|
3 | 1b | RW | 70-7F Enable (E70) Enables decoding of 1MB of the following BIOS range: |
2 | 1b | RW | 60-6F Enable (E60) Enables decoding of 1MB of the following BIOS range: |
1 | 1b | RW | 50-5F Enable (E50) Enables decoding of 1MB of the following BIOS range: |
0 | 1b | RW | 40-4F Enable (E40) Enables decoding of 1MB of the following BIOS range: |