Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Device Idle Control (DEVIDLE_CONTROL) – Offset 24c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:5 | - | - | Reserved
|
4 | 0h | RO | Interrupt Request Capable (intr_req_capable) Set to ‘1’ by HW if it is capable of generating an interrupt on command completion, else ‘0’. |
3 | 1h | RW/1C | Restore Required (restore_required) When set (by HW), SW must restore state to the controller. The state may have been lost due to a reset or full power lost. SW clears the bit by writing a ‘1’. This bit will be set on initial power up. |
2 | 0h | RW | Device Idle (devidle) SW sets this bit to ‘1’ to move the function into the DevIdle state. Writing this bit to ‘0’ will return the function to the fully active D0 state (D0i0). |
1 | - | - | Reserved
|
0 | 0h | RO | CMD In Progress (cmd_in_progress) HW sets this bit on a 1->0 or 0->1 transition of DEVIDLE. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register.HW clears this bit upon completing the DevIdle transition command. |