Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
PCI Status & Command (STATUSCOMMAND) – Offset 4
STATUSCOMMAND- Status and Command
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30 | - | - | Reserved
|
29 | 0h | RW/1C | Received Master Abort (RMA) The software writes a 1 to this bit to clear it. |
28 | 0h | RW/1C | Received Target Abort (RTA) The software writes a 1 to this bit to clear it. |
27:21 | - | - | Reserved
|
20 | 1h | RO | Capabilities List (CAPLIST) Indicates that the controller contains a capabilities pointer list. |
19 | 0h | RO | Interrupt Status (INTR_STATUS) This bit reflects state of interrupt in the device. |
18:11 | - | - | Reserved
|
10 | 0h | RW | Interrupt Disable (INTR_DISABLE) Setting this bit disables INTx assertion. |
9 | - | - | Reserved
|
8 | 0h | RW | (Reserved)
|
7:3 | - | - | Reserved
|
2 | 0h | RW | Bus Master Enable (BME) 0 = the Bridge does not generate any new upstream transaction onIOSF as a master. |
1 | 0h | RW | Memory Space Enable (MSE) MSE is part of the Type PCI configuration space eachdevice has. |
0 | - | - | Reserved
|