Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
| ID | Date | Version | Classification |
|---|---|---|---|
| 615146 | 08/09/2019 | 1.2 | Public |
Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
Keyboard and Text (KT) Additional Configuration
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
SATA MXTBA
SDXC (SD Card) PCR
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped
8254 Timer
Counter 0 - Interval Timer Status Byte Format Register (C0_ITSBFR)
Counter 2 - Interval Timer Status Byte Format Register (C2_ITSBFR)
Timer Control Word Register (TCW)
Counter 0 - Counter Access Ports Register (C0_CAPR)
Counter 2 - Counter Access Ports Register (C2_CAPR)
Read Back Command (RBC)
Counter Latch Command (CLC)
APIC Indirect
Identification Register (ID)
Version Register (VER)
Redirection Table Entry 0 (RTE0)
Redirection Table Entry 1 (RTE1)
Redirection Table Entry 2 (RTE2)
Redirection Table Entry 3 (RTE3)
Redirection Table Entry 4 (RTE4)
Redirection Table Entry 5 (RTE5)
Redirection Table Entry 6 (RTE6)
Redirection Table Entry 7 (RTE7)
Redirection Table Entry 8 (RTE8)
Redirection Table Entry 9 (RTE9)
Redirection Table Entry 10 (RTE10)
Redirection Table Entry 11 (RTE11)
Redirection Table Entry 12 (RTE12)
Redirection Table Entry 13 (RTE13)
Redirection Table Entry 14 (RTE14)
Redirection Table Entry 15 (RTE15)
Redirection Table Entry 16 (RTE16)
Redirection Table Entry 17 (RTE17)
Redirection Table Entry 18 (RTE18)
Redirection Table Entry 19 (RTE19)
Redirection Table Entry 20 (RTE20)
Redirection Table Entry 21 (RTE21)
Redirection Table Entry 22 (RTE22)
Redirection Table Entry 23 (RTE23)
Redirection Table Entry 24 (RTE24)
Redirection Table Entry 25 (RTE25)
Redirection Table Entry 26 (RTE26)
Redirection Table Entry 27 (RTE27)
Redirection Table Entry 28 (RTE28)
Redirection Table Entry 29 (RTE29)
Redirection Table Entry 30 (RTE30)
Redirection Table Entry 31 (RTE31)
Redirection Table Entry 32 (RTE32)
Redirection Table Entry 33 (RTE33)
Redirection Table Entry 34 (RTE34)
Redirection Table Entry 35 (RTE35)
Redirection Table Entry 36 (RTE36)
Redirection Table Entry 37 (RTE37)
Redirection Table Entry 38 (RTE38)
Redirection Table Entry 39 (RTE39)
Redirection Table Entry 40 (RTE40)
Redirection Table Entry 41 (RTE41)
Redirection Table Entry 42 (RTE42)
Redirection Table Entry 43 (RTE43)
Redirection Table Entry 44 (RTE44)
Redirection Table Entry 45 (RTE45)
Redirection Table Entry 46 (RTE46)
Redirection Table Entry 47 (RTE47)
Redirection Table Entry 48 (RTE48)
Redirection Table Entry 49 (RTE49)
Redirection Table Entry 50 (RTE50)
Redirection Table Entry 51 (RTE51)
Redirection Table Entry 52 (RTE52)
Redirection Table Entry 53 (RTE53)
Redirection Table Entry 54 (RTE54)
Redirection Table Entry 55 (RTE55)
Redirection Table Entry 56 (RTE56)
Redirection Table Entry 57 (RTE57)
Redirection Table Entry 58 (RTE58)
Redirection Table Entry 59 (RTE59)
Redirection Table Entry 60 (RTE60)
Redirection Table Entry 61 (RTE61)
Redirection Table Entry 62 (RTE62)
Redirection Table Entry 63 (RTE63)
Redirection Table Entry 64 (RTE64)
Redirection Table Entry 65 (RTE65)
Redirection Table Entry 66 (RTE66)
Redirection Table Entry 67 (RTE67)
Redirection Table Entry 68 (RTE68)
Redirection Table Entry 69 (RTE69)
Redirection Table Entry 70 (RTE70)
Redirection Table Entry 71 (RTE71)
Redirection Table Entry 72 (RTE72)
Redirection Table Entry 73 (RTE73)
Redirection Table Entry 74 (RTE74)
Redirection Table Entry 75 (RTE75)
Redirection Table Entry 76 (RTE76)
Redirection Table Entry 77 (RTE77)
Redirection Table Entry 78 (RTE78)
Redirection Table Entry 79 (RTE79)
Redirection Table Entry 80 (RTE80)
Redirection Table Entry 81 (RTE81)
Redirection Table Entry 82 (RTE82)
Redirection Table Entry 83 (RTE83)
Redirection Table Entry 84 (RTE84)
Redirection Table Entry 85 (RTE85)
Redirection Table Entry 86 (RTE86)
Redirection Table Entry 87 (RTE87)
Redirection Table Entry 88 (RTE88)
Redirection Table Entry 89 (RTE89)
Redirection Table Entry 90 (RTE90)
Redirection Table Entry 91 (RTE91)
Redirection Table Entry 92 (RTE92)
Redirection Table Entry 93 (RTE93)
Redirection Table Entry 94 (RTE94)
Redirection Table Entry 95 (RTE95)
Redirection Table Entry 96 (RTE96)
Redirection Table Entry 97 (RTE97)
Redirection Table Entry 98 (RTE98)
Redirection Table Entry 99 (RTE99)
Redirection Table Entry 100 (RTE100)
Redirection Table Entry 101 (RTE101)
Redirection Table Entry 102 (RTE102)
Redirection Table Entry 103 (RTE103)
Redirection Table Entry 104 (RTE104)
Redirection Table Entry 105 (RTE105)
Redirection Table Entry 106 (RTE106)
Redirection Table Entry 107 (RTE107)
Redirection Table Entry 108 (RTE108)
Redirection Table Entry 109 (RTE109)
Redirection Table Entry 110 (RTE110)
Redirection Table Entry 111 (RTE111)
Redirection Table Entry 112 (RTE112)
Redirection Table Entry 113 (RTE113)
Redirection Table Entry 114 (RTE114)
Redirection Table Entry 115 (RTE115)
Redirection Table Entry 116 (RTE116)
Redirection Table Entry 117 (RTE117)
Redirection Table Entry 118 (RTE118)
Redirection Table Entry 119 (RTE119)
CNVi PCI Configuration
Vendor and Device ID (CNVI_WIFI_VEN_DEV_ID)
Device Command and Status (CNVI_WIFI_PCI_COM_STAT)
Class Code and Revision ID (CNVI_WIFI_PCI_CLASS_CODE)
Base Address Register BAR0 Low (CNVI_WIFI_BAR0)
Base Address Register BAR0 High (CNVI_WIFI_BAR1)
Subsystem ID (CNVI_WIFI_SUBSYS_ID)
Capabilities Pointer (CNVI_WIFI_CAP_PTR)
Interrupt (CNVI_WIFI_INTERRUPT)
PCI Express Capabilities (CNVI_WIFI_GIO_CAP)
Device Capabilities (CNVI_WIFI_GIO_DEV_CAP)
Device Control Register (CNVI_WIFI_GIO_DEV)
Device Control 2 (CNVI_WIFI_GIO_DEV_CAP_2)
Device Control (CNVI_WIFI_GIO_DEV_2)
MSIX Capability (CNVI_WIFI_MSIX_CAP_HEAD)
MSIX Capability Structure (CNVI_WIFI_MSIX_TABLE_OFFSET)
MSIX Capability Structure (CNVI_WIFI_MSIX_PBA_OFFSET)
Power Management Capabilities (CNVI_WIFI_PMC)
Power Management Status and Control (CNVI_WIFI_PMCSR)
Capability ID and Message Control (CNVI_WIFI_MSI_MSG_CTRL)
MSI Low Address (CNVI_WIFI_MSI_LOW_ADD)
MSI High Address (CNVI_WIFI_MSI_HIGH_ADD)
MSI Data (CNVI_WIFI_MSI_DATA)
Uncorrectable Error Status Register (CNVI_WIFI_UNCORRECT_ERR_STAT)
Uncorrectable Error mask Register (CNVI_WIFI_UNCORRECT_ERR_MASK)
Uncorrectable Error Severity (CNVI_WIFI_UNCORRECT_ERR_SEV)
Error Status (CNVI_WIFI_CORRECT_ERR_STAT)
Error Mask (CNVI_WIFI_CORRECT_ERR_MASK)
Advanced Error Capabilities and Control (CNVI_WIFI_ADVANCED_ERR_CAP)
Header Log 1 (CNVI_WIFI_HEADER_LOG1)
Header Log 2 (CNVI_WIFI_HEADER_LOG2)
Header Log 3 (CNVI_WIFI_HEADER_LOG3)
Header Log 4 (CNVI_WIFI_HEADER_LOG4)
Device Serial Number Capability (CNVI_WIFI_GIO_SERIAL_CAP)
Serial Number Low (CNVI_WIFI_GIO_SERIAL_LOW)
Serial Number Upper (CNVI_WIFI_GIO_SERIAL_UP)
Header of LTR Extended Capability (CNVI_WIFI_LTR_EXTND_CAP_HEAD)
No Snoop Request (CNVI_WIFI_LTR_MAX_SNOOP_NOSNOOP_LAT)
L1 substates Extended Capability Header (CNVI_WIFI_L1PM_SUB_EXTND_CAP_HEAD)
L1 Substates Capability (CNVI_WIFI_L1PM_SUB_CAP)
L1 Substates Control (CNVI_WIFI_L1PM_SUB_CNTRL)
L1 Substates Control 2 (CNVI_WIFI_L1PM_SUB_CNTRL2)
Vendor Specific Capability Header (CNVI_WIFI_VEN_SPEC_CAP)
Vendor Specific Extended Capability (CNVI_WIFI_VEN_SPEC_EXTND_CAP)
SW LTR Pointer (CNVI_WIFI_LTP_PTR)
DevIdle Pointer (CNVI_WIFI_DEV_IDLE_PTR)
DevIdle Power on Latency (CNVI_WIFI_DEV_IDLE_PWR)
EMMC Additional
Software LTR Value (SW_LTR_val)
Auto LTR Value (Auto_LTR_val)
Capabilities Bypass (Cap_byps)
Capabilities Bypass 1 (Cap_byps_reg1)
Capabilities Bypass Register II (Cap_byps_reg2)
Device Idle D0i3 (reg_D0i3)
Tx CMD Delay Control (Tx_CMD_dly)
Tx Delay Control 1 (Tx_DATA_dly_1)
Tx Delay Control 2 (Tx_DATA_dly_2)
Rx CMD Data Delay Control 1 (Rx_CMD_Data_dly_1)
Rx Strobe Delay Control (Rx_Strobe_Ctrl_Path)
Rx CMD Data Path Delay Control 2 (Rx_CMD_Data_dly_2)
Master DLL Software Control (Master_Dll)
Auto Tuning Value (Auto_tuning)
EMMC Memory Mapped
SDMA System Address (sdmasysaddr)
Block Size (blocksize)
Block Count Register (blockcount)
Argument 1 (argument1)
Transfer Mode Register (transfermode)
Command (command)
Response (Response 0 And 1)
Response 2 (response2)
Response 3 (response3)
Response 4 (response4)
Response 5 (response5)
Response 6 (response6)
Response 6 (response7)
Buffer Data Port Register (dataport)
Present State (PRESENTSTATE)
Host Control 1 (hostcontrol1)
Power Control Register (powercontrol)
Block Gap Control Register (blockgapcontrol)
Wakeup Control (wakeupcontrol)
Clock Control (clockcontrol)
Timeout Control (timeoutcontrol)
Software Reset (softwarereset)
Normal Interrupt Status (normalintrsts)
Error Interrupt Status (errorintrsts)
Normal Interrupt Status Enable (normalintrstsena)
Error Interrupt Status Enable (errorintrstsena)
Normal Interrupt Signal Enable (normalintrsigena)
Error Interrupt Signal Enable (errorintrsigena)
Auto CMD12 Error Status (autocmderrsts)
Host Control 2 (hostcontrol2)
Capabilities (capabilities)
Maximum Current Capabilities (maxcurrentcap)
Force Event for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus)
Force Event Register for Error Interrupt Status (forceeventforerrintsts)
ADMA Error Status (admaerrsts)
ADMA System Address Register 1 (admasysaddr01)
ADMA System Address Register2 (admasysaddr2)
Preset Value for Initialization (presetvalue0)
Preset Value for Default Speed (presetvalue1)
Preset Value for High Speed (presetvalue2)
Preset Value for SDR12 (presetvalue3)
Preset Value for SDR25 (presetvalue4)
Preset Value for SDR50 (presetvalue5)
Preset Value for SDR104 (presetvalue6)
Preset Value for DDR50 (presetvalue7)
Boot Timeout Control (boottimeoutcnt)
Slot Interrupt Status (slotintrsts)
EMMC PCI Configuration
Device & Vendor ID (DEVVENDID)
PCI Status & Command (STATUSCOMMAND)
Rev ID & Class Code (REVCLASSCODE)
Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)
Base Address Low (BAR0)
Base Address Register high (BAR0_HIGH)
Base Address Register1 (BAR1)
(BAR1_HIGH)
Subsystem Vendor ID (SUBSYSTEMID)
(EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
Power Management Capability ID Register (POWERCAPID)
Power Management Control and Status Register (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
Device Vendor Specific (DEVID_VEND_SPECIFIC_REG)
SW LTR update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE Pointer Register (DEVICE_IDLE_POINTER_REG)
DOI3 Max Power & PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose PCI RW Register1 (GEN_REGRW1)
General Purpose PCI RW Register2 (GEN_REGRW2)
General Purpose PCI RW Register3 (GEN_REGRW3)
General Purpose PCI RW Register4 (GEN_REGRW4)
General Input Register (GEN_INPUT_REG)
Enhanced SPI (eSPI) PCI Configuration
Identifiers (ESPI_DID_VID)
Device Status and Command (ESPI_STS_CMD)
Class Code and Revision ID (ESPI_CC_RID)
Sub System Identifiers (ESPI_SS)
Capability List Pointer (ESPI_CAPP)
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE)
eSPI Generic I/O Range 1 (ESPI_LGIR1)
eSPI Generic I/O Range 2 (ESPI_LGIR2)
eSPI Generic I/O Range 3 (ESPI_LGIR3)
eSPI Generic I/O Range 4 (ESPI_LGIR4)
USB Legacy Keyboard/Mouse Control (ESPI_ULKMC)
eSPI Generic Memory Range (ESPI_LGMR)
BIOS Decode Enable (ESPI_BDE)
BIOS Control (ESPI_BC)
eSPI PCR
eSPI Slave Configuration Register And Link Control (SLV_CFG_REG_CTL)
eSPI Slave Configuration Register Data (SLV_CFG_REG_DATA)
Peripheral Channel Error for Slave 0 (PCERR_SLV0)
Virtual Wire Channel Error for Slave 0 (VWERR_SLV0)
Flash Access Channel Error for Slave 0 (FCERR_SLV0)
Link Error for Slave 0 (LNKERR_SLV0)
FIA Configuration PCR
Common Control (CC)
PCIe* Device Reference Clock Request Mapping 1 (DRCRM1)
PCIe* Device Reference Clock Request Mapping 2 (DRCRM2)
Device Reference Clock Request Mapping 3 (DRCRM3)
Strap Configuration 1 (STRPFUSECFG1)
HSIO Lane Owner Status 1 (LOS1)
HSIO Lane Owner Status 2 (LOS2)
GbE Configuration
GbE Vendor and Device Identification Register (GBE_VID_DID)
PCI Command & Status Register (PCICMD_STS)
Revision Identification & Class Code Register (RID_CC)
Cache Line Size Primary Latency Timer & Header Type Register (CLS_PLT_HEADTYP)
Memory Base Address Register A (MBARA)
Subsystem Vendor & Subsytem ID (DMI_CONFIG11)
Expansion ROM Base Address Register (ERBA)
Capabilities List Pointer Register (CAPP)
Interrupt Information & Maximum Latency/Minimum GrantRegister (INTR_MLMG)
LAN Disable Control (LANDISCTRL)
Lock LAN Disable (LOCKLANDIS)
System Time Control High Register (LTRCAP)
Capabilities List and Power Managment Capabilities Register (CLIST1_PMC)
PCI Power Management Control Status & Data Register (PMCS_DR)
Capabilities List 2 & Message Control Register (CLIST2_MCTL)
Message Address Low Register (MADDL)
Message Address High Register (MADDH)
Message Data Register (MDAT)
GbE Memory Mapped I/O
Gigabit Ethernet Capabilities and Status (GBECSR_00)
Gigabit Ethernet Capabilities and Status (GBECSR_18)
Gigabit Ethernet Capabilities and Status (GBECSR_20)
Gigabit Ethernet Capabilities and Status (GBECSR_F00)
Gigabit Ethernet Capabilities and Status F10 (GBECSR_F10)
Gigabit Ethernet Capabilities and Status (GBECSR_5400)
Gigabit Ethernet Capabilities and Status (GBECSR_5404)
Gigabit Ethernet Capabilities and Status (GBECSR_5800)
Gigabit Ethernet Capabilities and Status (GBECSR_5B54)
Generic SPI (GSPI) Additional
CLOCKS (CLOCKS)
RESETS (RESETS)
ACTIVE LTR (ACTIVELTR_VALUE)
Idle LTR Value (IDLELTR_VALUE)
TX Bit Count (TX_BIT_COUNT)
Rx Bit Count (RX_BIT_COUNT)
DMA Finish Disable (SSP_REG)
SPI CS CONTROL (SPI_CS_CONTROL)
reg_SW_Scratch_0 (SW_SCRATCH)
Clock Gate (CLOCK_GATE)
Remap Address Low (REMAP_ADDR_LO)
Remap Address High (REMAP_ADDR_HI)
Device Idle Control (DEVIDLE_CONTROL)
Delay Rx Clock (DEL_RX_CLK)
Capabilities (CAPABLITIES)
Generic SPI (GSPI) DMA Controller
CH 1 Linked List Pointer Low (LLP_LO1)
CH 1 Linked List Pointer High (LLP_HI1)
Raw Interrupt Status (RawTfr)
DMA Transfer Source Address Low (SAR_LO0)
DMA Transfer Source Address High (SAR_HI0)
DMA Transfer Destination Address Low (DAR_LO0)
DMA Transfer Destination Address High (DAR_HI0)
CH 0 Linked List Pointer Low (LLP_LO0)
CH 0 Linked List Pointer High (LLP_HI0)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Control Register Low (CTL_LO0)
Control Register High (CTL_HI0)
Source Status (SSTAT0)
Destination Status (DSTAT0)
Source Status Address Low (SSTATAR_LO0)
Source Status Address High (SSTATAR_HI0)
Destination Status Address Low (DSTATAR_LO0)
Destination Status Address High (DSTATAR_HI0)
DMA Transfer Configuration Low (CFG_LO0)
DMA Transfer Configuration High (CFG_HI0)
Source Gather (SGR0)
Destination Scatter (DSR0)
Raw Status for Error Interrupts (RawErr)
Interrupt Status (StatusTfr)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status register (StatusInt)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
GPIO Community 0
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_2)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_A_0)
Pad Ownership (PAD_OWN_GPP_A_1)
Pad Ownership (PAD_OWN_GPP_A_2)
Pad Ownership (PAD_OWN_GPP_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_5)
Pad Ownership (PAD_OWN_GPP_B_1)
Pad Ownership (PAD_OWN_GPP_B_2)
Pad Ownership (PAD_OWN_GPP_G_0)
Pad Configuration Lock (PADCFGLOCK_GPP_A_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0)
Pad Configuration Lock (PADCFGLOCK_GPP_B_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_8)
Pad Configuration Lock (PADCFGLOCK_GPP_G_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_G_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_G_0)
GPI Interrupt Status (GPI_IS_GPP_A_0)
GPI Interrupt Status (GPI_IS_GPP_B_0)
GPI Interrupt Status (GPI_IS_GPP_G_0)
GPI Interrupt Enable (GPI_IE_GPP_A_0)
GPI Interrupt Enable (GPI_IE_GPP_B_0)
GPI Interrupt Enable (GPI_IE_GPP_G_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_G_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G_0)
SMI Status (GPI_SMI_STS_GPP_B_0)
SMI Enable (GPI_SMI_EN_GPP_B_0)
NMI Status (GPI_NMI_STS_GPP_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_7)
NMI Enable (GPI_NMI_EN_GPP_B_0)
GPIO Community 1
SMI Status (GPI_SMI_STS_GPP_D_0)
SMI Enable (GPI_SMI_EN_GPP_D_0)
NMI Status (GPI_NMI_STS_GPP_D_0)
NMI Enable (GPI_NMI_EN_GPP_D_0)
PWM Control (PWMC)
GPIO Serial Blink Enable (GP_SER_BLINK)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_D_0)
Pad Ownership (PAD_OWN_GPP_D_1)
Pad Ownership (PAD_OWN_GPP_D_2)
Pad Ownership (PAD_OWN_GPP_F_0)
Pad Ownership (PAD_OWN_GPP_F_1)
Pad Ownership (PAD_OWN_GPP_F_2)
Pad Ownership (PAD_OWN_GPP_H_0)
Pad Ownership (PAD_OWN_GPP_H_1)
Pad Ownership (PAD_OWN_GPP_H_2)
Pad Configuration Lock (PADCFGLOCK_GPP_D_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0)
GPIO Serial Blink Command/Status (GP_SER_CMDSTS)
GPIO Serial Blink Data (GP_SER_DATA)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_2)
Pad Configuration Lock (PADCFGLOCK_GPP_F_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0)
Pad Configuration Lock (PADCFGLOCK_GPP_H_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)
Host Software Pad Ownership (HOSTSW_OWN_vGPIO_1)
GPI Interrupt Status (GPI_IS_GPP_D_0)
GPI Interrupt Status (GPI_IS_GPP_F_0)
GPI Interrupt Status (GPI_IS_GPP_H_0)
GPI Interrupt Status (GPI_IS_vGPIO_1)
GPI Interrupt Enable (GPI_IE_GPP_D_0)
GPI Interrupt Enable (GPI_IE_GPP_F_0)
GPI Interrupt Enable (GPI_IE_GPP_H_0)
GPI Interrupt Enable (GPI_IE_vGPIO_1)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)
GPI General Purpose Events Status (GPI_GPE_STS_vGPIO_1)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)
GPI General Purpose Events Enable (GPI_GPE_EN_vGPIO_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_23)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_0)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_3)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_30)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_31)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_32)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_33)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_34)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_35)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_36)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_37)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_39)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_2)
GPIO Community 2
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_DSW_0)
Pad Ownership (PAD_OWN_DSW_1)
Pad Configuration Lock (PADCFGLOCK_DSW_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)
Pad Configuration DW2 (PAD_CFG_DW2_GPD_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)
Host Software Pad Ownership (HOSTSW_OWN_DSW_0)
GPI Interrupt Enable (GPI_IE_DSW_0)
GPI General Purpose Events Status (GPI_GPE_STS_DSW_0)
GPI General Purpose Events Enable (GPI_GPE_EN_DSW_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)
GPIO Community 3
Pad Configuration DW0 (PAD_CFG_DW0_HDA_BCLK)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_RSTB)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SYNC)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SDO)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SDI_0)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SDI_1)
Pad Configuration DW0 (PAD_CFG_DW0_SSP1_SFRM)
Pad Configuration DW0 (PAD_CFG_DW0_SSP1_TXD)
GPIO Community 4
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_21)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_C_0)
Pad Ownership (PAD_OWN_GPP_C_1)
Pad Ownership (PAD_OWN_GPP_C_2)
Pad Ownership (PAD_OWN_GPP_E_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_0)
Pad Ownership (PAD_OWN_GPP_E_1)
Pad Ownership (PAD_OWN_GPP_E_2)
Pad Configuration Lock (PADCFGLOCK_GPP_C_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0)
Pad Configuration Lock (PADCFGLOCK_GPP_E_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_21)
Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)
GPI Interrupt Status (GPI_IS_GPP_C_0)
GPI Interrupt Status (GPI_IS_GPP_E_0)
GPI Interrupt Enable (GPI_IE_GPP_C_0)
GPI Interrupt Enable (GPI_IE_GPP_E_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)
SMI Status (GPI_SMI_STS_GPP_C_0)
SMI Status (GPI_SMI_STS_GPP_E_0)
NMI Status (GPI_NMI_STS_GPP_C_0)
NMI Status (GPI_NMI_STS_GPP_E_0)
NMI Enable (GPI_NMI_EN_GPP_C_0)
NMI Enable (GPI_NMI_EN_GPP_E_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_17)
GSPI PCI Configuration
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address (BAR)
Base Address High (BAR_HIGH)
Base Address 1 (BAR1)
Base Address 1 High (BAR1_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
Power Management Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
SW LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE Pointer (DEVICE_IDLE_POINTER_REG)
Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write 1 (GEN_REGRW1)
General Purpose Read Write 2 (GEN_REGRW2)
General Purpose Read Write 3 (GEN_REGRW3)
General Purpose Read Write 4 (GEN_REGRW4)
General Purpose Input (GEN_INPUT_REG)
High Definition Audio (D31:F3) Memory Mapped I/O
Global Capabilities (GCAP)
Minor Version (VMIN)
Major Version (VMAJ)
Output Payload Capability (OUTPAY)
Input Payload Capability (INPAY)
Global Control (GCTL)
Wake Enable (WAKEEN)
Processing Pipe Capability Header (PPCH)
Processing Pipe Control (PPCTL)
Processing Pipe Status (PPSTS)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC0LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC0LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC0LDPL)
Wake Status (WAKESTS)
Global Status (GSTS)
Global Capabilities 2 (GCAP2)
Linked List Capabilities Header (LLCH)
Output Stream Payload Capability (OUTSTRMPAY)
Input Stream Payload Capability (INSTRMPAY)
Interrupt Control (INTCTL)
Interrupt Status (INTSTS)
Wall Clock Counter (WALCLK)
Stream Synchronization (SSYNC)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC0LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC1LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC1LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC1LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC1LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC2LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC2LLPU)
CORB Lower Base Address (CORBLBASE)
CORB Upper Base Address (CORBUBASE)
CORB Write Pointer (CORBWP)
CORB Read Pointer (CORBRP)
CORB Control (CORBCTL)
CORB Status (CORBSTS)
CORB Size (CORBSIZE)
RIRB Lower Base Address (RIRBLBASE)
RIRB Upper Base Address (RIRBUBASE)
RIRB Write Pointer (RIRBWP)
Response Interrupt Count (RINTCNT)
RIRB Control (RIRBCTL)
RIRB Status (RIRBSTS)
RIRB Size (RIRBSIZE)
Immediate Command (IC)
Immediate Response (IR)
Immediate Command Status (ICS)
DMA Position Lower Base Address (DPLBASE)
DMA Position Upper Base Address (DPUBASE)
Input/Output Stream Descriptor x Control (ISD0CTL)
Input/Output Stream Descriptor x Status (ISD0STS)
Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIB)
Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL)
Input/Output Stream Descriptor x Last Valid Index (ISD0LVI)
Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)
Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS)
Input/Output Stream Descriptor x Format (ISD0FMT)
Input/Output Stream Descriptor x FIFO Limit (ISD0FIFOL)
Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA)
Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC8LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC8LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC8LDPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC0CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC0FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC0LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC0LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC1CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC1FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC1LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC1LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC2CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC2FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC2LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC2LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC3CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC3FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC3LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC3LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC4CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC4FMT)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC2LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC2LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC3LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC3LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC3LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC3LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC4LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC4LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC4LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC5CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC5FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC5LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC5LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC6CTL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC4LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC4LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC4LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC5LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC5LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC5LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC5LDPU)
Input/Output Processing Pipe's Link Connection x Format (IPPLC6FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC6LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC6LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC0CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC0FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC0LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC0LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC1CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC1FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC1LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC1LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC2CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC2FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC2LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC2LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC3CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC3FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC3LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC3LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC4CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC4FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC4LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC4LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC5CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC5FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC5LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC5LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC6CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC6FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC6LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC6LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC7CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC7FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC7LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC7LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC8CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC8FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC8LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC8LLPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC7LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC7LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC7LDPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC6LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC6LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC6LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC6LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC0LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC0LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC0LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC7LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC8LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC8LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC8LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC8LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC9LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC9LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC0LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC1LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC1LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC1LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC1LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC2LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC2LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC9LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC9LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC10LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC10LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC10LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC10LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC11LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC11LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC11LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC11LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC12LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC12LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC12LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC12LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC13LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC13LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC13LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC13LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC14LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC14LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC14LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC14LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC9LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC9LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC9LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC9LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC10LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC10LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC10LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC10LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC11LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC11LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC11LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC11LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC12LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC12LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC12LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC12LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC13LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC13LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC13LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC13LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC14LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC14LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC14LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC14LDPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC7CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC7FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC7LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC7LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC8CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC8FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC8LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC8LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC9CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC9FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC9LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC9LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC10CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC10FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC10LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC10LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC11CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC11FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC11LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC11LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC12CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC12FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC12LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC12LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC13CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC13FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC13LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC13LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC14CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC14FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC14LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC14LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC9CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC9FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC9LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC9LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC10CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC10FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC10LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC10LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC11CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC11FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC11LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC11LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC12CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC12FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC12LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC12LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC13CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC13FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC13LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC13LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC14CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC14FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC14LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC14LLPU)
Multiple Links Capability Header (MLCH)
Multiple Links Capability Declaration (MLCD)
Link x Capabilities (LCAP0)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC2LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC2LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC3LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC3LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC3LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC3LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC4LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC4LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC4LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC4LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC5LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC5LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC5LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC5LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC6LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC6LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC6LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC6LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC7LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC7LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC7LDPL)
Link 0 Control (LCTL0)
Link 1 Control (LCTL1)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC7LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC8LLPL)
High Definition Audio (D31:F3) PCI Configuration
Vendor Identification (VID)
Device ID (DID)
Command (CMD)
Status (STS)
Revision Identification (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Latency Timer (LT)
Header Type (HTYPE)
Intel HD Audio Base Lower Address (HDALBA)
Intel HD Audio Base Upper Address (HDAUBA)
Shadowed PCI Configuration Lower Base Address (SPCLBA)
Shadowed PCI Configuration Upper Base Address (SPCUBA)
Audio DSP Lower Base Address (ADSPLBA)
Audio DSP Upper Base Address (ADSPUBA)
Subsystem Vendor ID (SVID)
Subsystem ID (SID)
Capability Pointer (CAPPTR)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Power Gating Control (PGCTL)
Clock Gating Control (CGCTL)
PCI Power Management Capability ID (PID)
Power Management Capabilities (PC)
Power Management Control And Status (PCS)
Message Signal Interrupt Message Control (MMC)
MSI Message Lower Address (MMLA)
MSI Message Upper Address (MMUA)
MSI Message Data (MMD)
PCI Express Capability ID (PXID)
PCI Express Capabilities (PXC)
Device Capabilities (DEVCAP)
Device Control (DEVC)
Device Status (DEVS)
I2C Additional
Soft Reset (RESETS)
Active LTR (ACTIVELTR_VALUE)
Idle LTR (IDLELTR_VALUE)
TX Ack Count (TX_ACK_COUNT)
RX ACK Count (RX_BYTE_COUNT)
Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)
Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)
SW Scratch Register 0 (SW_SCRATCH_0)
SW Scratch Register 1 (SW_SCRATCH_1)
SW Scratch Register 2 (SW_SCRATCH_2)
SW Scratch Register 3 (SW_SCRATCH_3)
Clock Gate (CLOCK_GATE)
Remap Address Low (REMAP_ADDR_LO)
Remap Address High (REMAP_ADDR_HI)
Device Control (DEVIDLE_CONTROL)
Capabilities (CAPABLITIES)
I2C DMA Controller
DMA Transfer Source Address Low (SAR_LO0)
DMA Transfer Source Address High (SAR_HI0)
DMA Transfer Destination Address Low (DAR_LO0)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Raw Status for Error Interrupts (RawErr)
Interrupt Status (StatusTfr)
DMA Transfer Destination Address High (DAR_HI0)
CH 0 Linked List Pointer Low (LLP_LO0)
CH 0 Linked List Pointer High (LLP_HI0)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Control Register Low (CTL_LO0)
Control Register High (CTL_HI0)
Source Status (SSTAT0)
Destination Status (DSTAT0)
Source Status Address Low (SSTATAR_LO0)
Source Status Address High (SSTATAR_HI0)
Destination Status Address Low (DSTATAR_LO0)
Destination Status Address High (DSTATAR_HI0)
DMA Transfer Configuration Low (CFG_LO0)
DMA Transfer Configuration High (CFG_HI0)
Source Gather (SGR0)
Destination Scatter (DSR0)
CH 1 Linked List Pointer Low (LLP_LO1)
CH 1 Linked List Pointer High (LLP_HI1)
Raw Interrupt Status (RawTfr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status register (StatusInt)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
I2C Memory Mapped
I2C Control (IC_CON)
I2C Target Address (IC_TAR)
I2C High Speed Master Mode Code Address (IC_HS_MADDR)
I2C Rx/Tx Data Buffer and Command (IC_DATA_CMD)
Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)
Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)
Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)
Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)
High Speed I2C Clock SCL High Count (IC_HS_SCL_HCNT)
High Speed I2C Clock SCL Low Count (IC_HS_SCL_LCNT)
I2C Interrupt Status (IC_INTR_STAT)
I2C Interrupt Mask (IC_INTR_MASK)
I2C Raw Interrupt Status (IC_RAW_INTR_STAT)
I2C Receive FIFO Threshold (IC_RX_TL)
I2C Transmit FIFO Threshold (IC_TX_TL)
Clear Combined and Individual Interrupt (IC_CLR_INTR)
Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)
Clear RX_OVER Interrupt (IC_CLR_RX_OVER)
Clear TX_OVER Interrupt (IC_CLR_TX_OVER)
Clear RD_REQ Interrupt (IC_CLR_RD_REQ)
Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)
Clear RX_DONE Interrupt (IC_CLR_RX_DONE)
Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)
Clear STOP_DET Interrupt (IC_CLR_STOP_DET)
Clear START_DET Interrupt (IC_CLR_START_DET)
Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)
I2C Enable (IC_ENABLE)
I2C Status (IC_STATUS)
I2C Transmit FIFO Level (IC_TXFLR)
I2C Receive FIFO Level (IC_RXFLR)
I2C SDA Hold Time Length (IC_SDA_HOLD)
I2C Transmit Abort Source (IC_TX_ABRT_SOURCE)
DMA Control (IC_DMA_CR)
DMA Transmit Data Level (IC_DMA_TDLR)
I2C Receive Data Level (IC_DMA_RDLR)
I2C ACK General Call (IC_ACK_GENERAL_CALL)
I2C Enable Status (IC_ENABLE_STATUS)
I2C SS and FS Spike Suppression Limit (IC_FS_SPKLEN)
Clear RESTART_DET Interrupt (IC_CLR_RESTRART_DET)