Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Error Interrupt Status (errorintrsts) – Offset 32
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14:13 | - | - | Reserved
|
12 | 0h | RW/1C | Target Response Error (errorintrsts_hosterror) Occurs when detecting ERROR in DMA transaction |
11:10 | - | - | Reserved
|
9 | 0h | RW | ADMA Error (errorintrsts_admaerror) This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register. |
8 | 0h | RW | Auto CMD Error (errorintrsts_autocmderror) This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from0 to 1. |
7 | 0h | RW | Current Limit Error (errorintrsts_currlimiterror) By setting the SD Bus Power bit in the Power ControlRegister, the HC is requested to supply power for the SD Bus. |
6 | 0h | RW | Data End Bit Error (errorintrsts_dataendbiterror) Occurs when detecting 0 at the end bit position of readdata which uses the DAT line or the end bit position ofthe CRC status. |
5 | 0h | RW | Data CRC Error (errorintrsts_datacrcerror) Occurs when detecting CRC error when transferring readdata which uses the DAT line or when detecting theWrite CRC Status having a value of other than “010”. |
4 | 0h | RW | Data Timeout Error (errorintrsts_datatimeouterror) Occurs when detecting one of following timeoutconditions. |
3 | 0h | RW | Command Index Error (errorintrsts_cmdindexerror) Occurs if a Command Index error occurs in the Command Response. |
2 | 0h | RW | Command End Bit Error (errorintrsts_cmdendbiterror) Occurs when detecting that the end bit of a commandresponse is 0. |
1 | 0h | RW | Command CRC Error (errorintrsts_cmdcrcerror) 0 - No Error |
0 | 0h | RW | Command Timeout Error (errorintrsts_cmdtimeouterror) Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. |