Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Link Capabilities (LCAP) – Offset 4c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 00h | RO/V | Port Number (PN) Indicates the port number for the root port. This value is different for each implemented port: |
23 | - | - | Reserved
|
22 | 1b | RW/O | ASPM Optionality Compliance (ASPMOC) ASPM Optionality Compliance(ASPMOC): This bit must be set to 1b for PCIe 3.0 compliant port. |
21 | 1b | RO | Link Bandwidth Notification Capability (LBNC) This port supports Link Bandwidth Notification status and interrupt mechanisms. |
20 | 1b | RO | Link Active Reporting Capable (LARC) This port supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. |
19 | 0b | RO | Surprise Down Error Reporting Capable (SDERC) Set to '0 to indicate the root port does not support Surprise Down Error Reporting |
18 | 0b | RO | Clock Power Management (CPM) '0 Indicates that root ports do not support the CLKREQ# mechanism. |
17:15 | 010b | RW/O | L1 Exit Latency (EL1) Indicates an exit latency of 2us to 4us. |
14:12 | 000b | RO/V | L0s Exit Latency (EL0) Indicates an exit latency based upon common-clock configuration: |
11:10 | 11b | RW/O | Active State Link PM Support (APMS) Indicates the level of active state power management on this link |
9:4 | 000000b | RO/V | Maximum Link Width (MLW) For the root ports, several values can be taken, based upon the value of the chipset configuration register field RPC.PC1 for ports 1-4: |
3:0 | 0h | RO/V | Max Link Speeds (MLS) Indicates the supported link speeds of the Root Port |