Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
RFW (RFW) – Offset 78
Receive FIFO Write
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:10 | - | - | Reserved
|
9 | 0h | WO | RFFE (RFFE) Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. |
8 | 0h | WO | RFPE (RFPE) Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. |
7:0 | 0h | WO | RFWD (RFWD) Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled(FAR[0] is set to one). When FIFOs are enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. |