Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Chipset Initialization Register DA0 (CIRDA0) – Offset 1da0
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:28 | - | - | Reserved
|
27:24 | 6h | RW/L | Power Ungate Stall Latency (PUG_STALL_LTCY) When power ungating, this is the minimum time required between the deassertion of an Agent's pmc_ip_pg_ack_b signal before starting to handle another Power Gate/Ungate request. |
23:12 | - | - | Reserved
|
11:8 | 6h | RW/L | Power Gate Stall Latency (PG_STALL_LTCY) When power gating, this is the minimum time required between seeing an Agent's |
7:4 | - | - | Reserved
|
3:0 | 6h | RW/L | Power Gate PG Ack to PFET En Latency (PG_PGACK_PFETEN_LTCY) When power gating, this is the minimum time required between the assertion of an Agent's |