Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG) – Offset 80ec
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 03h | RW | Force LTSSM State (FORCE_LTSSM_ST) LTSSM state to be forced |
26 | 0b | RW | Direct Link LTSSM State (DL_LTSSM_ST) 0: Normal operation mode |
25 | 0b | RW | Direct Link To U0 (DL_U0) 0: Normal operation mode |
24:21 | 0h | RW | Forced Compliance Pattern (FORCED_CMP_PAT) Compliance pattern to be forced to enter compliance mode |
20:17 | - | - | Reserved
|
16:15 | 0h | RW | PHY Low Power Latency (PHY_LP_LAT) This field defines the latency to drive the PHY to enter low power mode |
14:12 | 0h | RW | Link Recovery Minimum Time (LR_MIN_TM) This value defines the minimum time for the link to stay in Recovery.Active other than from U3. The granuity is 128us. |
11:9 | 0h | RW | Link Polling Minimum Time (LP_MIN_TM) This value defines the minimum time for the link to stay in Polling.Active and Recovery.Active from U3. The granuity is 128us. |
8 | 0b | RW | Force Link Accept PM Command (FORCE_LA_PMC) 0: Normal operation mode |
7 | 0b | RW | Direct Link Recovery U0 (DL_REC_U0) 0: Normal operation mode |
6 | 0b | RW | Link Fast Training Mode (LINK_FTM) 0: Normal operation mode |
5 | 0b | RW | Disable Link Scrambler (DIS_LINK_SCRAM) 0: Enable link scrambler |
4 | 0b | RW | Direct Link U3 From U0 (DL_U3_U0) 0: Normal operation mode |
3 | 0b | RW | Direct Link U3 From U0 (DL_U2_U0) 0: Normal operation mode |
2 | 0b | RW | Direct Link U3 From U0 (DL_U1_U0) 0: Normal operation mode |
1 | 0b | RW | Enable Link Loopback Master Mode (EN_LINK_LB_MAST) 0: Disable link loopback master mode |
0 | 0b | RW | Disable Link Compliance Mode (DIS_LINK_CM) 0: Enable link compliance mode |