Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Port Control and Status (PCS) – Offset 94
By default, the SATA ports are set (by hardware) to the disabled state (e.g. bits[5:0] == '0') as a result of an initial power on reset. When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. When disabled, the port is in the off state and cannot detect any devices. Note: This register is not reset by FLR. Note: AHCI specific notes: If an AHCI-aware or RAID enabled operating system is being booted then system BIOS shall insure that all supported SATA ports are enabled prior to passing control to the OS. Once the AHCI aware OS is booted it becomes the enabling/disabling policy owner for the individual SATA ports. This is accomplished by manipulating a port's PxSCTL.DET and PxCMD.SUD fields. Because an AHCI or RAID aware OS will typically not have knowledge of the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-boot software must insure that these bits are set to '1' prior to booting the OS, regardless as to whether or not a device is currently on the port.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:19 | - | - | Reserved
|
18 | 0h | RO/V | Port 2 Present (P2P) Same definition as bit 16 (P0P), except this bit is for Port 2. |
17 | 0h | RO/V | Port 1 Present (P1P) Same definition as bit 16 (P0P), except this bit is for Port 1. |
16 | 0h | RO/V | Port 0 Present (P0P) This bit is set when COMINIT is received as a response to COMRESET. |
15:3 | - | - | Reserved
|
2 | 0h | RW/V | Port 2 Enabled (P2E) 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. |
1 | 0h | RW/V | Port 1 Enabled (P1E) 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. |
0 | 0h | RW/V | Port 0 Enabled (P0E) 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. |