Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
I2C SS and FS Spike Suppression Limit (IC_FS_SPKLEN) – Offset a0
This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS or FS modes.
The relevant I2Crequirement is tSP as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:8 | - | - | Reserved
|
7:0 | 07h | RW | IC_FS_SPKLEN (IC_FS_SPKLEN) This register must be set before any I2C bus transaction can take place toensure stable operation. This register sets the duration, measured in ic_clkcycles, of the longest spike in the SCL or SDA lines that are filtered out bythe spike suppression logic. |