Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Present State (PRESENTSTATE) – Offset 24
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:29 | - | - | Reserved
|
28:25 | fh | RO | DAT4 Line Signal Level (sdif_dat4in_dsync) sdif_dat4in_dsync |
24 | 1h | RO | CMD Line Signal Level (sdif_cmdin_dsync) This status is used to check CMD line level to recoverfrom errors, and for debugging |
23:20 | fh | RO | DAT0 Line Signal Level (sdif_dat0in_dsync) This status is used to check DAT line level to recover from errors, and for debugging. |
19 | 0h | RO | Write Protect Switch Pin Level (sdif_wp_dsync) The Write Protect Switch is supported for memory andcombo cards. This bit reflects the SDWP# pin.0 - Write protected (SDWP# = 0) |
18 | 0h | RO | Card Level Detect (sdif_cd_n_dsync) This bit reflects the inverse value of the SDCD# pin. |
17 | 0h | RO | Card State Stable (sdhccarddet_statestable_dsync) This bit is used for testing. If it is 0, the Card Detect PinLevel is not stable. If this bit is set to 1, it means theCard Detect Pin Level is stable. The Software Reset ForAll in the Software Reset Register shall not affect this bit. |
16 | 0h | RO | Card Inserted (sdhccarddet_inserted_dsync) This bit indicates whether a card has been inserted.Changing from 0 to 1 generates a Card InsertionInterrupt in the Normal Interrupt Status register andchanging from 1 to 0 generates a Card RemovalInterrupt in the Normal Interrupt Status register. |
15:12 | - | - | Reserved
|
11 | 0h | RO | Buffer Read Enable (sdhcdmactrl_piobufrdena) This status is used for non-DMA read transfers. |
10 | 0h | RO | Buffer Write Enable (sdhcdmactrl_piobufwrena) This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. |
9 | 0h | RO | Read Transfer Active (sdhcdmactrl_rdxferactive) This status is used for detecting completion of a read transfer.This bit is set to 1 for either of the following conditions: |
8 | 0h | RO | Write Transfer Active (sdhcdmactrl_wrxferactive) This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. |
7:4 | - | - | Reserved
|
3 | 0h | RO | Re-Tuning Request (Re-Tune) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the datawindow is shifted by temperature drift and any issue receiving the correct data. |
2 | 0h | RO | DATA line Active (Data Activity) This bit indicates whether one of the DAT line on SD busis in use.1 - DAT line active0 - DAT line inactive |
1 | 0h | RO | Command Inhibit (DAT) (presentstate_inhibitdat) This status bit is generated if either the DAT Line Activeor the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command.Commands with busy signal belong to Command Inhibit(DAT). |
0 | 0h | RO | Command Inhibit (CMD) (presentstate_inhibitcmd) If this bit is 0, it indicates the CMD line is not in use andthe HC can issue a SD command using the CMD line.This bit is set immediately after the Command register(00Fh) is written. This bit is cleared when the commandresponse is received. |