Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
I2C Control (IC_CON) – Offset 0
This register can be written only when the I2C is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:9 | - | - | Reserved
|
8 | 0h | RW | TX Empty Control (TX_EMPTY_CTRL) This bit controls the generation of the TX_EMPTY interrupt, asdescribed in the IC_RAW_INTR_STAT register. |
7 | - | - | Reserved
|
6 | 1h | RW | IC_SLAVE_DISABLE (IC_SLAVE_DISABLE) This bit controls whether I2C has its slave disabled.If this bit is set (slave is disabled), the function only works as a master and does not perform any action that requires a slave. |
5 | 1h | RO | Restart Enable (IC_RESTART_EN) Determines whether RESTART conditions may be sent when I2C is acting as a master. |
4 | 1h | RO | 7_10 Bit Addressing (IC_10BITADDR_MASTER_rd_only) Identifies if I2C operates in 7 or 10 bit addressing. |
3 | - | - | Reserved
|
2:1 | 3h | RW | Speed (SPEED) These bits control at which speed the I2C operates. |
0 | 1h | RW | Master Mode (MASTER_MODE) This bit controls whether I2C master is enabled. |