Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
GPI General Purpose Events Status (GPI_GPE_STS_vGPIO_1) – Offset 150
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:8 | - | - | Reserved
|
7 | 0b | RO | GPI General Purpose Events Status (GPI_GPE_STS_vGPIO_39) These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high (or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPI_GPE_EN register, then when the GPI_GPE_STS bit is set: If the system is in an S3-S5 state, the event will also wake the system. |
6:0 | - | - | Reserved
|