Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Source Gather (SGR0) – Offset 848
NOTE: SGR0 is for DMA Channel 0. The same register definition, SGR1, is available for Channel 1 at address 8A0h.
SGR0(CH0): offset 848h
SGR1(CH1): offset 8A0h
The Source Gather register contains two fields: Source gather count field (SGRx.SGC). Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary. Source gather interval field (SGRx.SGI). Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source transfer. The CTLx.SINC field controls whether the address increments or decrements. When the CTLx.SINC field indicates a fixed-address control, then the address remains constant throughout the transfer and the SGRx register is ignored.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:20 | 0h | RW | (SGC) Source gather count. Source contiguous transfer count between |
19:0 | 0h | RW | (SGI) Source gather interval. |