30:26 | - | - | Reserved |
25 | 0h | RO | DAT[7:4] Line Signal Level (host_regu_vol_stb) This status is used to check DAT line level to recover from errors, and for debugging. Bit 28 - DAT[7] Bit 27 - DAT[6] Bit 26 - DAT[5] Bit 25 - DAT[4] |
24 | 1h | RO | CMD Line Signal Level (sdif_cmdin_dsync) This status is used to check CMD line level to recover from errors, and for debugging |
23:20 | fh | RO | DAT[3:0] Line Signal Level (sdif_dat0in_dsync) This status is used to check DAT line level to recover from errors, and for debugging. Bit 23 - DAT[3] Bit 22 - DAT[2] Bit 21 - DAT[1] Bit 20 - DAT[0] |
19 | 0h | RO | Write Protect Switch Pin Level (sdif_wp_dsync) The Write Protect Switch is supported for memory and combo cards. This bit reflects the SDWP# pin. 0 - Write protected (SDWP# = 0) 1 - Write enabled (SDWP# = 1) |
18 | 0h | RO | Card Level Detect (sdif_cd_n_dsync) This bit reflects the inverse value of the SDCD# pin. 0 - No Card present (SDCD# = 1) 1 - Card present (SDCD# = 0) |
17 | 0h | RO | Card State Stable (sdhccarddet_statestable_dsync) This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit. 0 - Reset of Debouncing 1 - No Card or Inserted |
16 | 0h | RO | Card Inserted (sdhccarddet_inserted_dsync) This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion Interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit. If a Card is removed while its power is on and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power. 0 - Reset or Debouncing or No Card 1 - Card Inserted |
15:12 | - | - | Reserved |
11 | 0h | RO | Buffer Read Enable (sdhcdmactrl_piobufrdena) This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt. 0 - Read Disable 1 - Read Enable |
10 | 0h | RO | Buffer Write Enable (sdhcdmactrl_piobufwrena) This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt. 0 - Write Disable 1 - Write Enable. |
9 | 0h | RO | Read Transfer Active (sdhcdmactrl_rdxferactive) This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: - After the end bit of the read command - When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer. This bit is cleared to 0 for either of the following conditions: - When the last data block as specified by block length is transferred to the system. - When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0. 1 - Transferring data 0 - No valid data |
8 | 0h | RO | Write Transfer Active (sdhcdmactrl_wrxferactive) This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: - After the end bit of the write command. - When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: - After getting the CRC status of the last datablock as specified by the transfer count (Single or Multiple) - After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy. 1 - transferring data 0 - No valid data |
7:4 | - | - | Reserved |
3 | 0h | RO | Re-Tuning Request (sdhcsdctrl_retuningreq_dsync) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting Execute Tuning in the Host Control 2 register.Changing of this bit from 0 to 1 generates Re-Tuning Event. Refer to Normal Interrupt registers for more detail. This bit isn't set to 1 if Sampling Clock Select in the Host Control 2 register is set to 0 (using fixed sampling clock). 1= Sampling clock needs re-tuning 0 = Fixed or well tuned sampling clock |
2 | 0h | RO | DAT line Active (sdhcdmactrl_datalineactive) This bit indicates whether one of the DAT line on SD bus is in use. 1 - DAT line active 0 - DAT line inactive |
1 | 0h | RO | Command Inhibit (DAT) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register. Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0. 1 - Cannot issue command which uses the DAT line 0 - Can issue command which uses the DAT line |
0 | 0h | RO | Command Inhibit (CMD) If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing AutoCMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by Command register. |