Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Input/Output Stream Descriptor x Control (ISD0CTL) – Offset 80
NOTE: This register definition applies to all of the following input and output streams at the corresponding offsets:
Input stream 0: offset 80h
Input stream 1: offset A0h
Input stream 2: offset C0h
Input stream 3: offset E0h
Input stream 4: offset 100h
Input stream 5: offset 120h
Input stream 6: offset 140h
Input stream 7: offset 280h
Input stream 8: offset 2A0h
Input stream 9: offset 2C0h
Input stream 10: offset 2E0h
Input stream 11: offset 300h
Input stream 12: offset 320h
Input stream 13: offset 340h
Input stream 14: offset 360h
Output stream 0: offset 160h
Output stream 1: offset 180h
Output stream 2: offset 1A0h
Output stream 3: offset 1C0h
Output stream 4: offset 1E0h
Output stream 5: offset 200h
Output stream 6: offset 220h
output stream 7: offset 240h
Output stream 8: offset 260h
Output stream 9: offset 380h
Output stream 10: offset 3A0h
Output stream 11: offset 3C0h
Output stream 12: offset 3E0h
Output stream 13: offset 400h
Output stream 14: offset 420h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23:20 | 0h | RW | Stream Number (STRM) This value reflects the Tag associated with the data being transferred on the link. |
19 | 0b | RO | Bidirectional Direction Control (DIR) This bit is only meaningful for Bidirectional streams. |
18 | 1b | RO | Traffic Priority (TP) Hardwired to 1 indicating that all streams will use VC1 if it is enabled throughout |
17:16 | 00b | RW/L | Stripe Control (STRIPE) Input Stream: |
15:6 | - | - | Reserved
|
5 | 0b | RW/V/L | FIFO Limit Change (FIFOLC) Writing a 1 to this bit indicates a new update to the FIFOL register has been made. |
4 | 0b | RW | Descriptor Error Interrupt Enable (DEIE) Controls whether an interrupt is generated when the Descriptor Error Status (DESE) bit is set. |
3 | 0b | RW | FIFO Error Interrupt Enable (FEIE) This bit controls whether the occurrence of a FIFO error (overrun for input or underrun |
2 | 0b | RW | Interrupt On Completion Enable (IOCE) This bit controls whether or not an interrupt occurs when a buffer completes with the IOC |
1 | 0b | RW/V | Stream Run (RUN) When set to 1 the DMA engine associated with this input stream will be enabled to transfer |
0 | 0b | RW/V | Stream Reset (SRST) Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers |