Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SMI / SCI Status (SMSCS) – Offset dc
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW/1C/V | Power Management SCI Status (PMCS) This bit is set if the root port PME control logic needs to generate an interrupt, and this interrupt has been routed to generate an SCI. |
30 | 0b | RW/1C/V | Hot Plug SCI Status (HPCS) This bit is set if the hot plug controller needs to generate an interrupt, and has this interrupt been routed to generate an SCI. |
29:5 | - | - | Reserved
|
4 | 0b | RW/1C/V | Hot Plug Link Active State Changed SMI Status (HPLAS) This bit is set when SLSTS.DLLSC transitions from '0' to '1', and MPC.HPME is set. When this bit is set, an SMI# will be generated. |
3:2 | - | - | Reserved
|
1 | 0b | RW/1C/V | Hot Plug Presence Detect SMI Status (HPPDM) This bit is set when SLSTS.PDC transitions from '0' to'1', and MPC.HPME is set. When this bit is set, an SMI# will be generated. |
0 | 0b | RW/1C/V | Power Management SMI Status (PMMS) This bit is set when RSTS.PS transitions from '0' to'1', and MPC.PMME is set. |