Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
L1 Sub-States Control 1 (L1SCTL1) – Offset 208
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 000b | RW | L1.2 LTR Threshold Latency ScaleValue (L12LTRTLSV) This field contains the L1.OFF LTR Threshold Latency Scale Value for this particular PCIe root port. The value in this field, together with L12LTRTLV is compared against both the snoop and non-snoop LTR values of the device. |
28:26 | - | - | Reserved
|
25:16 | 0000000000b | RW | L1.2 LTR Threshold Latency Value (L12OFFLTRTLV) This field contains the L1.2 LTR Threshold Latency Value for this particular PCIe root port. The value in this field, together with L12LTRTLSV is compared against both the snoop and non-snoop LTR values of the device. |
15:8 | 00h | RW | Common Mode Restore Time (CMRT) This is the Tcommon_mode time the PCIe root port needs to continue sending TS1 and refrain from sending TS2 in Recovery state to allow the TX common mode to be established prior to sending TS2. The timer starts from the time when the first TS1 has been sent and the receiver has detected un-squelch. The value in this field defines the time in micro-seconds. |
7:4 | - | - | Reserved
|
3 | 0b | RW | ASPM L1.1 Enabled (AL11E) When set, this bit indicates that ASPM L1.SNOOZ substates are enabled for ASPM. |
2 | 0b | RW | ASPM L1.2 Enable (AL12E) When set, this bit indicates that ASPM L1.OFF substates are enabled for PCI-PM. |
1 | 0b | RW | PCI-PM L1.SNOOZ Enable (PPL11E) When set, this bit indicates that PCI-PM L1.SNOOZ power management feature is enabled. If L1.OFF is enabled, L1.SNOOZ must also be enabled. |
0 | 0b | RW | PCI-PM L1.2 Enabled (PPL12E) When set, this bit indicates that PCI-PM L1.OFF power management feature is enabled. L1.OFF can only be enabled if the platform supports bi-directional CLKREQPLUS#. |