Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
DCI Control (ECTRL) – Offset 4
ExI Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:7 | - | - | Reserved
|
6 | 1h | RW | USB3 DBC Enable Indication (USB3DBCEN) This bit is used in conjunction with bit 5. |
5 | 1h | RW | USB2 DBC enable indication (USB2DBCEN) This bit is used in conjunction with bit 6. See bit 6 for details. |
4 | 0h | RW/L | Host DCI Enable (HEEN) 0 = Disable DCI |
3:1 | - | - | Reserved
|
0 | 0h | RW/1L | DCI Lock (HOST_EXI_EN_LOCK) When set, the Host DCI Enable bit is locked. |