Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SSP (GSPI) Control Register 1 (SSCR1) – Offset 4
The Enhanced SSP Control 1 registers contain bit fields that control various SSP functions. Bits must be set to the preferred value before enabling the Enhanced SSP. Note that Writes to reserved bits should be zeroes, and Read value of these bits are undetermined.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23 | 0b | RW | RWOT (RWOT) Receive With Out Transmit |
22 | 0b | RW | TRAIL (TRAIL) Trailing Byte |
21 | 0b | RW | TSRE (TSRE) Transmit Service Request Enable |
20 | 0b | RW | RSRE (RSRE) Receive Service Request Enable |
19 | 0b | RW | TINTE (TINTE) Receiver Time-out Interrupt Enable |
18:17 | - | - | Reserved
|
16 | 0b | RW | IFS (IFS) Invert Frame Signal0 = Frame signal (Chip Select) is active low |
15:5 | - | - | Reserved
|
4 | 0b | RW | SPH (SPH) Motorola SPI SSPSCLK phase setting |
3 | 0b | RW | SPO (SPO) Motorola SPI SSPSCLK polarity setting |
2 | - | - | Reserved
|
1 | 0b | RW | TIE (TIE) Transmit FIFO Interrupt Enable |
0 | 0b | RW | RIE (RIE) Receive FIFO Interrupt Enable |