31:24 | 32h | RW | GPIO Driver Mode Interrupt Select (GPDMINTSEL) IRQ globally for all pads (GPI_IS with corresponding GPI_IE enable). 0 = Interrupt Line 0 1 = Interrupt Line 1 ... 255 = Interrupt Line 255 |
23:20 | - | - | Reserved |
19:16 | 0100b | RW | GPIO Group to GPE_DW2 assignment encoding (GPE0_DW2) This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 2h = GPP_G[7:0] mapped to GPE[71:64]; GPE[95:72] not used. 3h = Reserved. 4h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 5h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 7h = GPP_H[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 8h = vGPIO39 (vSD_CD#) mapped to GPE bit 70. 9h = Reserved Ah = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used Bh - Ch = Reserved Dh = GPP_E[23:0] mapped to GPE[87:64]; GPE[95:88] not used. Eh - Fh = Reserved |
15:12 | 0011b | RW | GPIO Group to GPE_DW1 assignment encoding (GPE0_DW1) This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 2h = GPP_G[7:0] mapped to GPE[39:32]; GPE[63:40] not used. 3h = Reserved. 4h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 5h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 7h = GPP_H[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 8h = vGPIO39 (vSD_CD#) mapped to GPE bit 38. 9h = Reserved Ah = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used Bh - Ch = Reserved Dh = GPP_E[23:0] mapped to GPE[55:32]; GPE[63:56] not used. Dh = GPP_E[23:0] mapped to GPE[55:32]; GPE[63:56] not used. Eh - Fh = Reserved |
11:8 | 0010b | RW | GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0) This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 2h = GPP_G[7:0] mapped to GPE[7:0]; GPE[31:8] not used. 3h = Reserved. 4h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 5h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 7h = GPP_H[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 8h = vGPIO_39 (vSD_CD#) mapped to GPE bit 7. 9h = Reserved Ah = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used Bh - Ch = Reserved Dh = GPP_E[23:0] mapped to GPE[23:0]; GPE[31:24] not used Eh - Fh = Reserved |
7:2 | - | - | Reserved |
1 | 0b | RW | GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN) Specifies whether the GPIO Community should take part in partition clock gating 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating |
0 | 0b | RW | GPIO Dynamic Local Clock Gating Enable (GPDLCGEN) Specifies whether the GPIO Community should perform local clock gating. 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating |