Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
Redirection Table Entry 0 (RTE0) – Offset 10
The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message.
The APIC will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the I/O APIC is set. The state machine will step ahead and wait for an ackledgement from the APIC unit that the interrupt message was sent. Only then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new edge will only result in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request register bit to go from 0 to 1. (In other words, if the interrupt was not already pending a the destination.)
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
63:56 | 00h | RW | Destination ID (DID) If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an APIC ID. In this case, bits 63:59 should be programmed by software to 0. If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination address of a set of processors. |
55:48 | 00h | RW | Extended Destination ID (EDID) These bits are sent to a local APIC only when in Processor System Bus mode. They become bits 11:4 of the address. |
47:17 | - | - | Reserved
|
16 | 1b | RW | Mask (MSK) 0 = Not masked. An edge or level on this interrupt pin results in the delivery of the interrupt to the destination. |
15 | 0b | RW | Trigger Mode (TM) This field indicates the type of signal on the interrupt pin that triggers an interrupt. |
14 | 0b | RO/V | Remote IRR (RIRR) This is used for level triggered interrupts; its meaning is undefined for edge triggered interrupts. |
13 | 0b | RW | Polarity (POL) This bit specifies the polarity of each interrupt signal connected to the interrupt pins. |
12 | 0b | RO/V | Delivery Status (DS) This field contains the current status of the delivery of this interrupt. |
11 | 0b | RW | Destination Mode (DSM) This field is used by the local Apic to determine whether it is the destination of the message. |
10:8 | 000b | RW | Delivery Mode (DLM) This field specifies how the APICs listed in the destination field should act upon reception of this signal. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode. These encodings are: |
7:0 | 00h | RW | Vector (VCT) This field contains the interrupt vector for this interrupt. Values range between 10h and FEh. |