Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Alternate Protocol Capabilities Register (APCAPR) – Offset b10
This is the Alternate Protocol Capabilities Register registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:9 | 0h | RO | Reserved (RSVD_M) Reserved |
8 | 0h | RW/O | Alternate Protocol Selective Enable Supported (APSES) If Set, the Alternate Protocol Selective Enable Mask Register is present. |
7:0 | 0h | RW/L | Alternate Protocol Count (APC) Indicates the number of Alternate Protocols supported by one or more Lanes of this Link. |