Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_ICRRD_OPCODE) – Offset 1014
THC SPI Bus Read Opcode Register.
Note: The THC_M_PRT_SPI_ICRRD_OPCODE register can't be written/updated when TX/RX DMAs is
running or PIO is running cycles on the bus.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | bh | RW | Single IO Interrupt Cause Register Read SPI (SPI_SIO_ICRRD_OPCODE) Single IO Read (1-1-1) Opcode for the interrupt cause |
23:16 | bbh | RW | Dual IO Interrupt Cause Register Read SPI (SPI_DIO_ICRRD_OPCODE) Dual IO Read (1-2-2) Opcode for the interrupt cause |
15:8 | ebh | RW | Quad IO Interrupt Cause Register Read SPI (SPI_QIO_ICRRD_OPCODE) Quad IO Read (1-4-4) Opcode for the interrupt cause |
7:0 | fbh | RW | QPI Interrupt Cause Register Read SPI Opcode (SPI_QPI_ICRRD_OPCODE) QPI Read (4-4-4) Opcode for the interrupt cause |