Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
THC Interrupt Status Register (THC_M_PRT_INT_STATUS) – Offset 1024
THC Port Interrupt Status Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RO | Reserved (RSVD_31) Reserved. |
30 | 0h | RW/1C/V | Interrupt Status of THC fatal error (FATAL_ERR_INT_STS) Interrupt status when a THC fatal error occurs. If the THC_Fatal_Err_Intr_En bit is also 1, then an interrupt is generated. SW clears the bit by writing 1 to the bit. |
29 | 0h | RO | Reserved (RSVD_29) Reserved. |
28 | 0h | RW/1C/V | Interrupt Status of THC transaction error (TXN_ERR_INT_STS) Interrupt status when a THC transaction error occurs. If the THC_TXN_Err_Intr_En bit is also 1, then an interrupt is generated. SW clears the bit by writing 1 to the bit. |
27:0 | 0h | RO | Reserved (RSVD_27_0) Reserved. |