Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
GPI Interrupt Status (GPI_IS_GPP_A_0) – Offset 200
Refer to Register Field for detail
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:25 | 0h | RO | Reserved (RSVD_0)
|
24 | 0h | RO | Reserved |
23 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_23) Same description as bit 0 |
22 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_22) Same description as bit 0 |
21 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_21) Same description as bit 0 |
20 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_20) Same description as bit 0 |
19 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_19) Same description as bit 0 |
18 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_18) Same description as bit 0 |
17 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_17) Same description as bit 0 |
16 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_16) Same description as bit 0 |
15 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_15) Same description as bit 0 |
14 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_14) Same description as bit 0 |
13 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_13) Same description as bit 0 |
12 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_12) Same description as bit 0 |
11 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_11) Same description as bit 0 |
10 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_10) Same description as bit 0 |
9 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_9) Same description as bit 0 |
8 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_8) Same description as bit 0 |
7 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_7) Same description as bit 0 |
6 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_6) Same description as bit 0 |
5 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_5) Same description as bit 0 |
4 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_4) Same description as bit 0 |
3 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_3) Same description as bit 0 |
2 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_2) Same description as bit 0 |
1 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_1) Same description as bit 0 |
0 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_a_0) This bit is set to '1' by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: |