Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Port Power Management Status and Control USB2 (PORTPMSC1) – Offset 484
The register listed in this section is at offset 484h for USB2 Port 1.
There are the same registers available at offsets : 484h + (USB2 Port Number -1)*10h) for other USB2 ports. Specifically,
USB2 Port 1: 484h (shown below)
USB2 Port 2: 494h
USB2 Port 3: 4A4h
.....
USB2 Port 9: 504h
USB2 Port 10: 514h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:28 | 0h | RW/P | Port Test Control (PTC) When this field is ‘0’, the port is not operating in a test mode. (Default) A non-zero value indicates that the port is operating in test mode and the specific test mode is indicated by the specific value. A non-zero Port Test Control value is only valid to a port that is in the Disabled state. If the port is not in this state, the xHC shall respond with the Port Test Control field set to Port Test Control Error. |
27:17 | 0h | RO | Rsvd1 (RSVD1) Reserved |
16 | 0h | RW | Hardware LPM Enable (HLE) 0=disable |
15:8 | 0h | RW/P | Device Address (DA) Note: This register is sticky. |
7:4 | 0h | RW/P | Host Initiated Resume Duration (HIRD) Note: This register is sticky. |
3 | 0h | RW/P | Remote Wake Enable (RWE) The host system sets this flag to enable or disable the device for remote wake from L1. |
2:0 | 0h | RW | L1 Status (L1S) Note: This register is sticky. |