Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
GPI Interrupt Enable (GPI_IE_GPP_F_0) – Offset 214
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:26 | 0h | RO | Reserved (RSVD_0)
|
25:24 | 0h | RO | Reserved |
23 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_23) Same description as bit 0. |
22 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_22) Same description as bit 0. |
21 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_21) Same description as bit 0. |
20 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_20) Same description as bit 0. |
19 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_19) Same description as bit 0. |
18 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_18) Same description as bit 0. |
17 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_17) Same description as bit 0. |
16 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_16) Same description as bit 0. |
15 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_15) Same description as bit 0. |
14 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_14) Same description as bit 0. |
13 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_13) Same description as bit 0. |
12 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_12) Same description as bit 0. |
11 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_11) Same description as bit 0. |
10 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_10) Same description as bit 0. |
9 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_9) Same description as bit 0. |
8 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_8) Same description as bit 0. |
7 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_7) Same description as bit 0. |
6 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_6) Same description as bit 0. |
5 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_5) Same description as bit 0. |
4 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_4) Same description as bit 0. |
3 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_3) Same description as bit 0. |
2 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_2) Same description as bit 0. |
1 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_1) Same description as bit 0. |
0 | 0h | RW | GPI Interrupt Enable (GPI_INT_EN_xxgpp_f_0) This bit is used to enable/disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is set. |