Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG DEL_RX_CLK (DEL_RX_CLK) – Offset 250
MMIO bit per SPI Controller allows selection of the Delayed Rx Clock.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:2 | 0h | RO | Reserved |
1:0 | 0h | RW | RX_CLK_SEL (RX_CLK_SEL) 2'b00: The output of the internal (M/N and/or baud rate) clock divider is used as-is to clock in the receive data to the RxFIFO. |