Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Status (DEVS) – Offset 8a
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:7 | 0h | RO | Reserved (RSVD3) This is a Reserved Register |
6 | 0h | RO | Emergency Power Reduction Detected (EPRD) This bit is Set when the Function is in the Emergency Power Reduction State. |
5 | 0h | RO/V | Transactions Pending (TXP) A 1 indicates that the ACE IP has issued Non-Posted requests which have not been completed. A 0 indicates that Completions for all Non-Posted Requests have been received. |
4 | 1h | RO/V | AUX Power Detected (AUXDET) Hardwired to 1 indicating the device is connected to Primary power and able to wake from D3cold state. |
3 | 0h | RW/1C/V | Unsupported Request Detected (URDET) This bit indicates that the Function received an Unsupported Request |
2 | 0h | RO | Fatal Error Detected (FEDET) Not implemented. Hardwired to 0. |
1 | 0h | RW/1C/V | Non-Fatal Error Detected (NFEDET) This bit indicates status of Non-fatal errors detected |
0 | 0h | RO | Correctable Error Detected (CEDET) Not implemented. Hardwired to 0. |