Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE) – Offset 80
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 0h | RO | Reserved |
29 | 0h | RW | Microcontroller Enable #2 (ME2) Enables decoding of I/O locations 4Eh and 4Fh. |
28 | 0h | RW | SuperI/O Enable (SE) Enables decoding of I/O locations 2Eh and 2Fh. |
27 | 0h | RW | Microcontroller Enable #1 (ME1) Enables decoding of I/O locations 62h and 66h. |
26 | 0h | RW | Keyboard Enable (KE) Enables decoding of the keyboard I/O locations 60h and 64h. |
25 | 0h | RW | High Gameport Enable (HGE) Enables decoding of the I/O locations 208h to 20Fh. |
24 | 0h | RW | Low Gameport Enable (LGE) Enables decoding of the I/O locations 200h to 207h. |
23:20 | 0h | RO | Reserved |
19 | 0h | RW | Floppy Drive Enable (FDE) Enables decoding of the FDD range. Range is selected by LIOD.FDE |
18 | 0h | RW | Parallel Port Enable (PPE) Enables decoding of the LPT range. Range is selected by LIOD.LPT. |
17 | 0h | RW | Com Port B Enable (CBE) Enables decoding of the COMB range. Range is selected LIOD.CB. |
16 | 0h | RW | Com Port A Enable (CAE) Enables decoding of the COMA range. Range is selected LIOD.CA. |
15:13 | 0h | RO | Reserved |
12 | 0h | RW | FDD Range (FDD) The following table describes which range to decode for the FDD Port. Bits Decode Range: |
11:10 | 0h | RO | Reserved |
9:8 | 0h | RW | LPT Range (LPT) The following table describes which range to decode for the LPT Port: |
7 | 0h | RO | Reserved |
6:4 | 0h | RW | ComB Range (CB) The following table describes which range to decode for the COMB Port |
3 | 0h | RO | Reserved |
2:0 | 0h | RW | ComA Range (CA) The following table describes which range to decode for the COMA Port |