Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Management Status and Control (CNVI_WIFI_PMCSR) – Offset cc
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | dh | RO | Power Dissipation Control (PWR_DIS_CON) Used to report power consumption and heat dissipation (default for D3-0x1) |
23 | 0h | RO | BUS Power Clock Control Enable (BUS_PWR_CLK_CEN) Bus Power/Clock Control Enable, does not apply to PCI Express. Hardwired. |
22 | 0h | RO | B2 B3 Support (B2_B3_SUPRT) B2/B3 Support, does not apply to PCI Express. Hardwired. |
21:16 | 0h | RO | Reserved |
15 | 0h | RW/1C | PME Status (PME_STAT) This bit reflects whether the function has experienced a PME. Sticky value. |
14:13 | 0h | RO | Data Scale (DAT_SCALE) Data Scale |
12:9 | 0h | RW | Data Select (DAT_SEL) Data Select, selects the data value to be viewed through the Data register |
8 | 0h | RW | PME Enable (PME_ENA) PME Enable. Sticky value. |
7:4 | 0h | RO | Reserved |
3 | 1h | RO | No Soft Reset (NO_SOFT_RESET) No soft reset |
2 | 0h | RO | Reserved |
1:0 | 0h | RW | Power State (PWR_STATE) Power State |