Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SLP S0 DEBUG REG0 (SLP_S0_DBG_0) – Offset 10b4
This register captures the state of low power events involved in SLP_S0# entry to assist with debug. The status is captured as part of C10 entry(once CPU has entered package C10 ) or it can be captured by writing a 1 to LATCH_SLPS0_EVENTS bit in this register.Note that static or function disable status of the IP is incorporated in the individual status register bits though overrides / masks in CPPMVRIC* registers does not impact the value reflects in this register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW | Latch SLP_S0#events (LATCH_SLPS0_EVENTS) When this bit is written to 1, the current state of SLP_S0# events is latched and captured in SLP_S0_DEBUG_REGx registers. A write of 0 has no effect though it is necessary to clear this register before writing a 1 to latch events the next time. Note that writes to this register will bring CPU out of C10 and wake PLLs so its usage is limited to looking at certain low power entry events that are not affected by writes to this register. |
30:8 | 0h | RO | Reserved |
7 | 0h | RO/V | UFS1_D3_STS (UFS1_D3_STS) This bit when 1 indicates that UFS1 controller is in D3 state (taking static/function disables into account as well) |
6 | 0h | RO/V | UFS0_D3_STS (UFS0_D3_STS) This bit when 1 indicates that UFS0 controller is in D3 state (taking static/function disables into account as well) |
5 | 0h | RO/V | SATA_D3_STS (SATA_D3_STS) This bit when 1 indicates that SATA controller is in D3 state (taking static/function disables into account as well) |
4 | 0h | RO | Reserved |
3 | 0h | RO/V | LPIO_D3_STS (LPIO_D3_STS) This bit when 1 indicates that UART, GSPI, I2C controllers are in D3 state (taking static/function disables into account as well) |
2 | 0h | RO/V | XHCI_D3_STS (XHCI_D3_STS) This bit when 1 indicates that XHCI controller is in D3 state (taking static/function disables into account as well) |
1 | 0h | RO/V | OTG_D3_STS (OTG_D3_STS) This bit when 1 indicates that OTG controller is in D3 state (taking static/function disables into account as well) |
0 | 0h | RO/V | AUDIO_D3_STS (AUDIO_D3_STS) This bit when 1 indicates that Audio DSP controller is in D3 state (taking static/function disables into account as well) |