Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
GSX Channel-0 Test Mode (GSX_C0TM) – Offset 33c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:13 | 0h | RO | Reserved (RSVD_0)
|
12 | 0h | RW | Bit-bang GSXSRESET# (BBGSXSRESETB) This bit allows software to directly bit bang the GSXSRESET#. |
11 | 0h | RW | Bit-bang GSXSLOAD (BBGSXSLOAD) This bit allows software to directly bit bang the GSXSLOAD. |
10 | 0h | RW | Bit-bang GSXSDOUT (BBGSXSDOUT) This bit allows software to directly bit bang the GSXSDOUT. |
9 | 0h | RW | Bit-bang GSXSCLK (BBGSCLK) This bit allows software to directly bit bang the GSXSCLK. |
8 | 0h | RW | Bit-bang Enable (BBE) When this bit is '1', the bit-bang mode is enable and the CxTM.BBGSXS* register bits are directly controlling the GSX pins. |
7:1 | 0h | RW | Reserved (Reserved1)
|
0 | 0h | RW | Alternate SCLK Rate (ALTSCLK) This test mode allows slower toggle rate of the GSX channel. |