Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL) – Offset 2cc
i3c dev idle control register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:5 | 0h | RO | Reserved |
4 | 0h | RO | intr_req_capable (intr_req_capable) intr_req_capable, Set to 1 by HW if it is capable of generating an interrupt on command |
3 | 1h | RW/1C | restore_required (restore_required) When set (by HW), SW must restore state to the IP. The state may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. This bit will be set on initial power up. |
2 | 0h | RW | devidle (devidle) devidle, SW sets this bit to 1 to move the function into the DevIdle state. Writing this |
1 | 0h | RO | Reserved |
0 | 0h | RO | cmd_in_progress (cmd_in_progress) HW sets this bit on a 1->0 or 0->1 transition of DEVIDLE. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register. |