Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Revision ID (RID_CC) – Offset 8
This is the Revision ID registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 6h | RO | Base Class Code (BCC) Indicates the device is a bridge device. |
23:16 | 4h | RO/V | Sub-Class Code (SCC) The default indicates the device is a PCI-to-PCI bridge. If the MPC.Bridge Type register is set to a 1 for a Host Bridge, this register reads 00h. |
15:8 | 0h | RO/V | Programming Interface (PI) This field identifies a specific register level programming interface. |
7:0 | f0h | RO/V | Revision ID (RID) Indicates the revision of the bridge. |