Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
NMI Status (GPI_NMI_STS_GPP_B_0) – Offset 2b0
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:25 | 0h | RO | Reserved |
24 | 0h | RO | GPI NMI Status (GPI_NMI_STS_ishi3c0_clk_loopbk) This bit is set to '1' by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: The corresponding pad is used in GPIO input mode (PMode) The corresponding GPIONMIRout is set to '1', i.e. programmed to route as NMI The corresponding GPIOOwn[2:0] is '000' (i.e. ACPI GPIO Mode). The corresponding GPI_NMI_EN is set Writing a value of '1' will clear the bit while writing a value of '0' has no effect. 0 = There is no NMI event 1 = There is an NMI event Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 For pads which do not support NMI, the corresponding bit is read-only zero. \t\t\t |
23 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_b_23) Same description as bit 14. |
22:21 | 0h | RO | Reserved |
20 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_b_20) Same description as bit 14. |
19:15 | 0h | RO | Reserved |
14 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_b_14) This bit is set to '1' by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: |
13:0 | 0h | RO | Reserved |