Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
NMI Status (GPI_NMI_STS_GPP_E_0) – Offset 2b4
Refer to Register Field for detail
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:25 | 0h | RO | Reserved (RSVD_0)
|
24:17 | 0h | RO | Reserved |
16 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_16) Same description as bit 0. |
15 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_15) Same description as bit 0. |
14 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_14) Same description as bit 0. |
13 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_13) Same description as bit 0. |
12:9 | 0h | RO | Reserved |
8 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_8) Same description as bit 0. |
7 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_7) Same description as bit 0. |
6 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_6) Same description as bit 0. |
5 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_5) Same description as bit 0. |
4 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_4) Same description as bit 0. |
3 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_3) Same description as bit 0. |
2 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_2) Same description as bit 0. |
1 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_1) Same description as bit 0. |
0 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_e_0) This bit is set to '1' by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: |