Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SATA General Configuration (SATAGC) – Offset 9c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW/O | Register Lock (REGLOCK) BIOS can set this bit to 1 to lock the following registers with RW/L attribute: CAP,CP, MID.NEXT, PIE.NEXT, SATACR0.NEXT. Once locked the register attribute of above list changes from RW/L to RO holding the existing value. BIOS is required to program this field to 1 prior to handle off to OS. If BIOS needs the SATA host controller to change operation a few times (i.e. changing CC.SCC mode) and need different capability structures for each specific operation mode, BIOS need not activate the lock until BIOS is ready to hand off to OS. BIOS may need to separate write access to this byte offset (x9Fh) from write to the lower 3-byte of the dword (x9C-9Eh) if there is a need to program the lower 3-byte dword location early during boot process. This field is not reset by FLR. |
30:18 | 0h | RO | RSVD0 (RSVD0) Reserved |
17 | 0h | RW | Do_Serr Disable (DOSERRD) When 1,SERR reporting is disabled (DO_SERR Sideband message sending is disabled or SERR# Wire is supressed. STS.SSE setting is not governed by this policy bit). When 0, SERR reporting is enabled (DO_SERR Sideband message sending is enabled or SERR# Wire is not supressed). This register field is not reset by FLR. |
16 | 0h | RW | SATA Mode Select (SMS) Software (SW) programs these bits to control the mode in which the SATA HBA should operate: 0b = AHCI mode; 1b = RAID mode. |
15 | 0h | RW | Data Phase Parity Error Enable (DPPEE) When 1, IOSF data phase parity error handling is enabled. When 0, the data phase parity error handling is disabled. This register field is not reset by FLR. |
14:12 | 0h | RW | Write Request_Size Select/Max_Payload_Size (WRRSELMPS) These two bits select the max write request size that SATA host controller will initiate for DMA write to memory. SATA host controller will internally break up larger write request based on these bits. The request is address-aligned to the selected size. Defined encodings for this field are: 000b = 128 address aligned bytes max payload size; 111b = 64 address aligned bytes max payload size. All other values are reserved for SATA host controller. This field is not reset by FLR. |
11 | 0h | RW | Command Parity Error Enable (CPEE) When 1, command parity error handing is enabled. When 0, the command parity error handling is disabled. This field is not reset by FLR. |
10 | 0h | RW | SATA Controller Function Disable (SCFD) BIOS program this bit to 1 to disable the SATA Controller function. When 0, SATA Controller function is enabled. When disable, SATA Host Controller will not claimed the register access targeting its Configuration Space. In IOSF primary Fabric Decode scheme, it's expected BIOS also program the corresponding bit used by the Fabric Decoder accordingly hence both SATA SIP and Fabric Decoder are in sync, and BIOS need to program this bit before programming the one in Fabric Decoder. Once this bit is set, BIOS isnot able to revert it back to Function Enable until next round of platform reset. This register field is not reset by FLR. |
9 | 0h | RW | Unsupported Request Reporting Enable (URRE) If set to 1 by software, it allows reporting of an Unsupported Request as a system error. If both URRE and PCI configuration SERR# Enable registers are set to a 1, then the agent must set the Signaled System Error bit in the PCI Status register and send a DO_SERR message in IOSF-SB interface. |
8 | 0h | RW/1C/V | Unsupported Request Detected (URD) Set to 1 by hardware upon detecting an Unsupported Request on IOSF Primary interface that is not considered Advisory Non-Fatal. Cleared to 0 by SW. URD bit is only set based on IOSF primary bus interface activity. Its not set based on IOSF sideband bus interface activity. |
7 | 0h | RW/O | Alternate ID Enable (AIE) When programmed to 0, HW will report the following DID value to load the Windows* In-Box Driver. When programmed to a 1, SATA Host Controller will not report the DID value to load the Windows* In-Box Driver. Programming this bit to a 1 will prevent the Windows in-box version of the Intel AHCI driver from loading on the platform - will require that the user perform an 'F6' install of the Intel driver that is appropriate for the reported DID. This field is applicable when the AHCI is configured for RAID mode of operation. It has no impact for AHCI and IDE modes of operation. Note: BIOS is recommended to program this bit prior to programming the SATAGC.SMS field to reflect RAID. This field is reset by PLTRST# and BIOS is required to reprogram the value (either 0 or 1) after resuming from S3, S4 or S5. This insures that the value is properly and cannot be changed during runtime. This field is not reset by FLR. |
6 | 0h | RW/O/V | AIE0 DevID Selection (DEVIDSEL) This register allows BIOS to select Device ID when AIE=0. |
5 | 0h | RW/O | FLR Capability Selection (FLRCSSEL) This allows the FLR Capability to be bypassed. Refer to config offset B0h. BIOS is required to program this bit to 1 and config offset A8h SATACR0.NEXT to 00h. This field is not reset by FLR. |
4:3 | 0h | RW/O | MXTBA Size Select (MSS) These 2 bits select the size of the Memory space for the MSI-X Table defined in BAR 0 (Configuration space offset 10h). MSI-X Table Memory space size is 32k when MSS[1:0]=00, 16k when MSS[1:0]=01, 8k when MSS[1:0]=10. This field is not reset by FLR. |
2:0 | 0h | RW/O | ABAR Size Select (ASSEL) These 3 bits select the size of the Memory space for the ABAR in BAR 5 (Configuration space offset 24h). ABAR Memory space size is 2k when ASSEL[2:0]=000, 16k when ASSEL[2:0]=001, 32k when ASSEL[2:0]=010, 64k when ASSEL[2:0]=011, 128k when ASSEL[2:0]=100, 256k when ASSEL[2:0]=101, 512k when ASSEL[2:0]=110. This field is not reset by FLR. |