Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Management Capabilities (PM_CAP) – Offset 72
Normally, this register is read-only to report capabilities to the power management software. In order to report different power management capabilities depending on the system in which the SoC is used, the write access to this register is controlled by the Access Control bit (ACCTRL). The value written to this register does not affect the hardware other than changing the value returned during a read.
This register is modified and maintained by BIOS
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:11 | 18h | RW/L | PME Support (PME_SUPPORT) This 5-bit field indicates the power states in which the function may assert PME#. The Intel controller does not support the D1 or D2 states. For all other states, the XHC is capable of generating PME#. Software should never need to modify this field. |
10 | 0h | RW/L | D2 Support (D2_SUPPORT) The D2 state is not supported. |
9 | 0h | RW/L | D1 Support (D1_SUPPORT) The D1 state is not supported. |
8:6 | 7h | RW/L | Aux Current (AUX_CURRENT) The XHC reports 375mA maximum Suspend well current required when in the D3cold state. This value can be written by BIOS when a more accurate value is known. |
5 | 0h | RW/L | Device Specific Initialization (DSI) 0: indicating that no device-specific initialization is required. |
4 | 0h | RO | Reserved |
3 | 0h | RW/L | PME Clock (PMECLOCK) 0: indicating that no PCI clock is required to generate PME#. |
2:0 | 3h | RW/L | Version Indication (VERSION) 010: indicating that it complies with Revision 1.1 of the PCI Power Management Specification. |