Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Global Capabilities 2 (GCAP2) – Offset 12
This register indicates the additional capabilities of the controller.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:3 | 0h | RO | Reserved |
2 | 0h | RO | HD Audio Low Power Link Capability (LPLC) Indicates whether the HDA link is capable of low power operation with just the link DMA, whilst the host DMA is being reset with CRSTB = 0. |
1 | 0h | RO | Dynamic FIFO Limit Change Capability (DFIFOLCC) Indicates whether the energy efficient audio FIFOLC operation is static or dynamic. |
0 | 0h | RO | Energy Efficient Audio Capability (EEAC) Indicates whether the energy efficient audio with deeper buffering is supported or not. 0 = Not supported. FIFOL register and FIFOLC bit behave as RO. |