Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
I2C Target Address (IC_TAR) – Offset 4
The register should only be updated when the I2C is not enabled (IC_ENABLE=0) or No Master mode operations are active (IC_STATUS[5] = 0 and IC_CON[0] = 1 and IC_STATUS[2] = 1).
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:17 | 0h | RO | Reserved_17_31 (Reserved_17_31) Reserved |
16 | 0h | RO | Reserved_16_16 (Reserved_16_16) Reserved |
15:14 | 0h | RO | Reserved_14_15 (Reserved_14_15) Reserved |
13 | 0h | RO | Reserved_13_13 (Reserved_13_13) Reserved |
12 | 1h | RW | IC_10BITADDR_MASTER (IC_10BITADDR_MASTER) This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing mode when acting as a master. |
11 | 0h | RW | SPECIAL (SPECIAL) This bit indicates whether software performs a General Call or START BYTE command. |
10 | 0h | RW | GC_OR_START (GC_OR_START) If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C. |
9:0 | 55h | RW | IC_TAR (IC_TAR) This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. |