Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Link x Wall Frame Counter (LWALFC0) – Offset c58
This register indicates the total output payload available on specific link at 6 MHz.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:9 | 0h | RO/V | Frame Number (FN) 23 bit counter that is incremented when CIF rolls over from 499 to 0. This counter will roll over to zero with a period of approximately 174 seconds. |
8:0 | 0h | RO/V | Clock in Frame (CIF) 9 bit counter that is incremented on each link BCLK period and rolls over from 499 to 0. This counter will roll over to zero with a period of 48 KHz HD Audio frame.With the introduction of multiple link segments for the Intel HD Audio controller, and the capability of running each link segment at different clock speed, the BCLK definition is fixed at 24 MHz equivalent rate always, independent of the physical link clock speed. |