Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
PCI Command (PCICMD) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:11 | 0h | RO | Reserved |
10 | 0h | RO | Interrupt Disable (INTD) P2SB does not issue any interrupts on its own behalf |
9 | 0h | RO | Fast Back to Back Enable (FB2BE) Not applicable |
8 | 0h | RW | SERR# Enable (SEE) This will enable parity error reporting |
7 | 0h | RO | Reserved |
6 | 0h | RW | Parity Error Response Enable (PEE) This bit controls the device's response to parity error. |
5 | 0h | RO | VGA Palette Snoop (VGA) Not applicable. |
4 | 0h | RO | Memory Write & Invalidate Enable (MWIE) Not applicable. |
3 | 0h | RO | Special Cycle Enable (SCE) Not applicable. |
2 | 1h | RO | Bus Master Enable (BME) Bus mastering cannot be disabled as this device acts as a proxy for non-PCI devices. |
1 | 0h | RW | Memory Space Enable (MSE) Will control the P2SB acceptance of PCI MMIO BARs only. Other legacy regions are unaffected by this bit. |
0 | 0h | RW | I/O Space Enable (IOSE) Legacy regions are unaffected by this bit. |